#ifndef __LPDDR5_REGB_FREQ0_CH0_H__
#define __LPDDR5_REGB_FREQ0_CH0_H__

#include "main.h"

typedef struct __LPDDR5_REGB_FREQ0_CH0 {
	volatile uint32_t DRAMSET1TMG0;	 // offset: 0x0 default value: 0xf101b0f read mask: 0x0 write mask 0xffffffff
	volatile uint32_t DRAMSET1TMG1;	 // offset: 0x4 default value: 0x5080414 read mask: 0xc00000 write mask 0xff3fffff
	volatile uint32_t DRAMSET1TMG2;	 // offset: 0x8 default value: 0x305060d read mask: 0x80800000 write mask 0x7f7fffff
	volatile uint32_t DRAMSET1TMG3;	 // offset: 0xC default value: 0x40404 read mask: 0xff800000 write mask 0x7fffff
	volatile uint32_t DRAMSET1TMG4;	 // offset: 0x10 default value: 0x5040405 read mask: 0xc0c080 write mask 0xff3f3f7f
	volatile uint32_t DRAMSET1TMG5;	 // offset: 0x14 default value: 0x5050403 read mask: 0xc08080c0 write mask 0x3f7f7f3f
	volatile uint32_t DRAMSET1TMG6;	 // offset: 0x18 default value: 0x5 read mask: 0xffffffc0 write mask 0x3f
	volatile uint32_t DRAMSET1TMG7;	 // offset: 0x1C default value: 0x0 read mask: 0xfffffff0 write mask 0xf
	volatile uint32_t RSVD_0;	 // offset: 0x20 Reserved 0.
	volatile uint32_t DRAMSET1TMG9;	 // offset: 0x24 default value: 0x4040d read mask: 0xffe0c000 write mask 0x1f3fff
	volatile uint32_t RSVD_1;	 // offset: 0x28 Reserved 1.
    volatile uint32_t RSVD_2;	 // offset: 0x2c Reserved 2.
	volatile uint32_t DRAMSET1TMG12;	 // offset: 0x30 default value: 0x20000 read mask: 0xfff0ffff write mask 0xf0000
	volatile uint32_t DRAMSET1TMG13;	 // offset: 0x34 default value: 0x1c200004 read mask: 0x8080fff0 write mask 0x7f7f000f
	volatile uint32_t DRAMSET1TMG14;	 // offset: 0x38 default value: 0x800a0 read mask: 0xfe00f000 write mask 0x1ff0fff
	volatile uint32_t RSVD_3;	 // offset: 0x3c Reserved 3.
	volatile uint32_t RSVD_4;	 // offset: 0x40 Reserved 4.
	volatile uint32_t RSVD_5;	 // offset: 0x44 Reserved 5.
	volatile uint32_t RSVD_6;	 // offset: 0x48 Reserved 6.
	volatile uint32_t RSVD_7;	 // offset: 0x4c Reserved 7.
	volatile uint32_t RSVD_8;	 // offset: 0x50 Reserved 8.
	volatile uint32_t RSVD_9;	 // offset: 0x54 Reserved 9.
	volatile uint32_t RSVD_10;	 // offset: 0x58 Reserved 10.
	volatile uint32_t DRAMSET1TMG23;	 // offset: 0x5C default value: 0x0 read mask: 0xffffffff write mask 0xff0fff
	volatile uint32_t DRAMSET1TMG24;	 // offset: 0x60 default value: 0xf0f0f read mask: 0xfc000000 write mask 0x3ffffff
	volatile uint32_t DRAMSET1TMG25;	 // offset: 0x64 default value: 0x0 read mask: 0xfff80000 write mask 0x7ffff
	volatile uint32_t RSVD_11;	 // offset: 0x68 Reserved 11.
	volatile uint32_t RSVD_12;	 // offset: 0x6c Reserved 12.
	volatile uint32_t RSVD_13;	 // offset: 0x70 Reserved 13.
	volatile uint32_t RSVD_14;	 // offset: 0x74 Reserved 14.
	volatile uint32_t DRAMSET1TMG30;	 // offset: 0x78 default value: 0x0 read mask: 0xff000000 write mask 0xffffff
	volatile uint32_t RSVD_15;	 // offset: 0x7c Reserved 15.
	volatile uint32_t DRAMSET1TMG32;	 // offset: 0x80 default value: 0x30408 read mask: 0xfff0f0f0 write mask 0xf0f0f
	volatile uint32_t RSVD_16;	 // offset: 0x84 Reserved 16.
	volatile uint32_t RSVD_17;	 // offset: 0x88 Reserved 17.
	volatile uint32_t RSVD_18;	 // offset: 0x8c Reserved 18.
	volatile uint32_t RSVD_19;	 // offset: 0x90 Reserved 19.
	volatile uint32_t RSVD_20;	 // offset: 0x94 Reserved 20.
	volatile uint32_t RSVD_21;	 // offset: 0x98 Reserved 21.
	volatile uint32_t RSVD_22;	 // offset: 0x9c Reserved 22.
	volatile uint32_t RSVD_23;	 // offset: 0xa0 Reserved 23.
	volatile uint32_t RSVD_24;	 // offset: 0xa4 Reserved 24.
	volatile uint32_t RSVD_25;	 // offset: 0xa8 Reserved 25.
	volatile uint32_t RSVD_26;	 // offset: 0xac Reserved 26.
	volatile uint32_t RSVD_27;	 // offset: 0xb0 Reserved 27.
	volatile uint32_t RSVD_28;	 // offset: 0xb4 Reserved 28.
	volatile uint32_t RSVD_29;	 // offset: 0xb8 Reserved 29.
	volatile uint32_t RSVD_30;	 // offset: 0xbc Reserved 30.
	volatile uint32_t RSVD_31;	 // offset: 0xc0 Reserved 31.
	volatile uint32_t RSVD_32;	 // offset: 0xc4 Reserved 32.
	volatile uint32_t RSVD_33;	 // offset: 0xc8 Reserved 33.
	volatile uint32_t RSVD_34;	 // offset: 0xcc Reserved 34.
	volatile uint32_t RSVD_35;	 // offset: 0xd0 Reserved 35.
	volatile uint32_t RSVD_36;	 // offset: 0xd4 Reserved 36.
	volatile uint32_t RSVD_37;	 // offset: 0xd8 Reserved 37.
	volatile uint32_t RSVD_38;	 // offset: 0xdc Reserved 38.
	volatile uint32_t RSVD_39;	 // offset: 0xe0 Reserved 39.
	volatile uint32_t RSVD_40;	 // offset: 0xe4 Reserved 40.
	volatile uint32_t RSVD_41;	 // offset: 0xe8 Reserved 41.
	volatile uint32_t RSVD_42;	 // offset: 0xec Reserved 42.
	volatile uint32_t RSVD_43;	 // offset: 0xf0 Reserved 43.
	volatile uint32_t RSVD_44;	 // offset: 0xf4 Reserved 44.
	volatile uint32_t RSVD_45;	 // offset: 0xf8 Reserved 45.
	volatile uint32_t RSVD_46;	 // offset: 0xfc Reserved 46.
	volatile uint32_t RSVD_47;	 // offset: 0x100 Reserved 47.
	volatile uint32_t RSVD_48;	 // offset: 0x104 Reserved 48.
	volatile uint32_t RSVD_49;	 // offset: 0x108 Reserved 49.
	volatile uint32_t RSVD_50;	 // offset: 0x10c Reserved 50.
	volatile uint32_t RSVD_51;	 // offset: 0x110 Reserved 51.
	volatile uint32_t RSVD_52;	 // offset: 0x114 Reserved 52.
	volatile uint32_t RSVD_53;	 // offset: 0x118 Reserved 53.
	volatile uint32_t RSVD_54;	 // offset: 0x11c Reserved 54.
	volatile uint32_t RSVD_55;	 // offset: 0x120 Reserved 55.
	volatile uint32_t RSVD_56;	 // offset: 0x124 Reserved 56.
	volatile uint32_t RSVD_57;	 // offset: 0x128 Reserved 57.
	volatile uint32_t RSVD_58;	 // offset: 0x12c Reserved 58.
	volatile uint32_t RSVD_59;	 // offset: 0x130 Reserved 59.
	volatile uint32_t RSVD_60;	 // offset: 0x134 Reserved 60.
	volatile uint32_t RSVD_61;	 // offset: 0x138 Reserved 61.
	volatile uint32_t RSVD_62;	 // offset: 0x13c Reserved 62.
	volatile uint32_t RSVD_63;	 // offset: 0x140 Reserved 63.
	volatile uint32_t RSVD_64;	 // offset: 0x144 Reserved 64.
	volatile uint32_t RSVD_65;	 // offset: 0x148 Reserved 65.
	volatile uint32_t RSVD_66;	 // offset: 0x14c Reserved 66.
	volatile uint32_t RSVD_67;	 // offset: 0x150 Reserved 67.
	volatile uint32_t RSVD_68;	 // offset: 0x154 Reserved 68.
	volatile uint32_t RSVD_69;	 // offset: 0x158 Reserved 69.
	volatile uint32_t RSVD_70;	 // offset: 0x15c Reserved 70.
	volatile uint32_t RSVD_71;	 // offset: 0x160 Reserved 71.
	volatile uint32_t RSVD_72;	 // offset: 0x164 Reserved 72.
	volatile uint32_t RSVD_73;	 // offset: 0x168 Reserved 73.
	volatile uint32_t RSVD_74;	 // offset: 0x16c Reserved 74.
	volatile uint32_t RSVD_75;	 // offset: 0x170 Reserved 75.
	volatile uint32_t RSVD_76;	 // offset: 0x174 Reserved 76.
	volatile uint32_t RSVD_77;	 // offset: 0x178 Reserved 77.
	volatile uint32_t RSVD_78;	 // offset: 0x17c Reserved 78.
	volatile uint32_t RSVD_79;	 // offset: 0x180 Reserved 79.
	volatile uint32_t RSVD_80;	 // offset: 0x184 Reserved 80.
	volatile uint32_t RSVD_81;	 // offset: 0x188 Reserved 81.
	volatile uint32_t RSVD_82;	 // offset: 0x18c Reserved 82.
	volatile uint32_t RSVD_83;	 // offset: 0x190 Reserved 83.
	volatile uint32_t RSVD_84;	 // offset: 0x194 Reserved 84.
	volatile uint32_t RSVD_85;	 // offset: 0x198 Reserved 85.
	volatile uint32_t RSVD_86;	 // offset: 0x19c Reserved 86.
	volatile uint32_t RSVD_87;	 // offset: 0x1a0 Reserved 87.
	volatile uint32_t RSVD_88;	 // offset: 0x1a4 Reserved 88.
	volatile uint32_t RSVD_89;	 // offset: 0x1a8 Reserved 89.
	volatile uint32_t RSVD_90;	 // offset: 0x1ac Reserved 90.
	volatile uint32_t RSVD_91;	 // offset: 0x1b0 Reserved 91.
	volatile uint32_t RSVD_92;	 // offset: 0x1b4 Reserved 92.
	volatile uint32_t RSVD_93;	 // offset: 0x1b8 Reserved 93.
	volatile uint32_t RSVD_94;	 // offset: 0x1bc Reserved 94.
	volatile uint32_t RSVD_95;	 // offset: 0x1c0 Reserved 95.
	volatile uint32_t RSVD_96;	 // offset: 0x1c4 Reserved 96.
	volatile uint32_t RSVD_97;	 // offset: 0x1c8 Reserved 97.
	volatile uint32_t RSVD_98;	 // offset: 0x1cc Reserved 98.
	volatile uint32_t RSVD_99;	 // offset: 0x1d0 Reserved 99.
	volatile uint32_t RSVD_100;	 // offset: 0x1d4 Reserved 100.
	volatile uint32_t RSVD_101;	 // offset: 0x1d8 Reserved 101.
	volatile uint32_t RSVD_102;	 // offset: 0x1dc Reserved 102.
	volatile uint32_t RSVD_103;	 // offset: 0x1e0 Reserved 103.
	volatile uint32_t RSVD_104;	 // offset: 0x1e4 Reserved 104.
	volatile uint32_t RSVD_105;	 // offset: 0x1e8 Reserved 105.
	volatile uint32_t RSVD_106;	 // offset: 0x1ec Reserved 106.
	volatile uint32_t RSVD_107;	 // offset: 0x1f0 Reserved 107.
	volatile uint32_t RSVD_108;	 // offset: 0x1f4 Reserved 108.
	volatile uint32_t RSVD_109;	 // offset: 0x1f8 Reserved 109.
	volatile uint32_t RSVD_110;	 // offset: 0x1fc Reserved 110.
	volatile uint32_t RSVD_111;	 // offset: 0x200 Reserved 111.
	volatile uint32_t RSVD_112;	 // offset: 0x204 Reserved 112.
	volatile uint32_t RSVD_113;	 // offset: 0x208 Reserved 113.
	volatile uint32_t RSVD_114;	 // offset: 0x20c Reserved 114.
	volatile uint32_t RSVD_115;	 // offset: 0x210 Reserved 115.
	volatile uint32_t RSVD_116;	 // offset: 0x214 Reserved 116.
	volatile uint32_t RSVD_117;	 // offset: 0x218 Reserved 117.
	volatile uint32_t RSVD_118;	 // offset: 0x21c Reserved 118.
	volatile uint32_t RSVD_119;	 // offset: 0x220 Reserved 119.
	volatile uint32_t RSVD_120;	 // offset: 0x224 Reserved 120.
	volatile uint32_t RSVD_121;	 // offset: 0x228 Reserved 121.
	volatile uint32_t RSVD_122;	 // offset: 0x22c Reserved 122.
	volatile uint32_t RSVD_123;	 // offset: 0x230 Reserved 123.
	volatile uint32_t RSVD_124;	 // offset: 0x234 Reserved 124.
	volatile uint32_t RSVD_125;	 // offset: 0x238 Reserved 125.
	volatile uint32_t RSVD_126;	 // offset: 0x23c Reserved 126.
	volatile uint32_t RSVD_127;	 // offset: 0x240 Reserved 127.
	volatile uint32_t RSVD_128;	 // offset: 0x244 Reserved 128.
	volatile uint32_t RSVD_129;	 // offset: 0x248 Reserved 129.
	volatile uint32_t RSVD_130;	 // offset: 0x24c Reserved 130.
	volatile uint32_t RSVD_131;	 // offset: 0x250 Reserved 131.
	volatile uint32_t RSVD_132;	 // offset: 0x254 Reserved 132.
	volatile uint32_t RSVD_133;	 // offset: 0x258 Reserved 133.
	volatile uint32_t RSVD_134;	 // offset: 0x25c Reserved 134.
	volatile uint32_t RSVD_135;	 // offset: 0x260 Reserved 135.
	volatile uint32_t RSVD_136;	 // offset: 0x264 Reserved 136.
	volatile uint32_t RSVD_137;	 // offset: 0x268 Reserved 137.
	volatile uint32_t RSVD_138;	 // offset: 0x26c Reserved 138.
	volatile uint32_t RSVD_139;	 // offset: 0x270 Reserved 139.
	volatile uint32_t RSVD_140;	 // offset: 0x274 Reserved 140.
	volatile uint32_t RSVD_141;	 // offset: 0x278 Reserved 141.
	volatile uint32_t RSVD_142;	 // offset: 0x27c Reserved 142.
	volatile uint32_t RSVD_143;	 // offset: 0x280 Reserved 143.
	volatile uint32_t RSVD_144;	 // offset: 0x284 Reserved 144.
	volatile uint32_t RSVD_145;	 // offset: 0x288 Reserved 145.
	volatile uint32_t RSVD_146;	 // offset: 0x28c Reserved 146.
	volatile uint32_t RSVD_147;	 // offset: 0x290 Reserved 147.
	volatile uint32_t RSVD_148;	 // offset: 0x294 Reserved 148.
	volatile uint32_t RSVD_149;	 // offset: 0x298 Reserved 149.
	volatile uint32_t RSVD_150;	 // offset: 0x29c Reserved 150.
	volatile uint32_t RSVD_151;	 // offset: 0x2a0 Reserved 151.
	volatile uint32_t RSVD_152;	 // offset: 0x2a4 Reserved 152.
	volatile uint32_t RSVD_153;	 // offset: 0x2a8 Reserved 153.
	volatile uint32_t RSVD_154;	 // offset: 0x2ac Reserved 154.
	volatile uint32_t RSVD_155;	 // offset: 0x2b0 Reserved 155.
	volatile uint32_t RSVD_156;	 // offset: 0x2b4 Reserved 156.
	volatile uint32_t RSVD_157;	 // offset: 0x2b8 Reserved 157.
	volatile uint32_t RSVD_158;	 // offset: 0x2bc Reserved 158.
	volatile uint32_t RSVD_159;	 // offset: 0x2c0 Reserved 159.
	volatile uint32_t RSVD_160;	 // offset: 0x2c4 Reserved 160.
	volatile uint32_t RSVD_161;	 // offset: 0x2c8 Reserved 161.
	volatile uint32_t RSVD_162;	 // offset: 0x2cc Reserved 162.
	volatile uint32_t RSVD_163;	 // offset: 0x2d0 Reserved 163.
	volatile uint32_t RSVD_164;	 // offset: 0x2d4 Reserved 164.
	volatile uint32_t RSVD_165;	 // offset: 0x2d8 Reserved 165.
	volatile uint32_t RSVD_166;	 // offset: 0x2dc Reserved 166.
	volatile uint32_t RSVD_167;	 // offset: 0x2e0 Reserved 167.
	volatile uint32_t RSVD_168;	 // offset: 0x2e4 Reserved 168.
	volatile uint32_t RSVD_169;	 // offset: 0x2e8 Reserved 169.
	volatile uint32_t RSVD_170;	 // offset: 0x2ec Reserved 170.
	volatile uint32_t RSVD_171;	 // offset: 0x2f0 Reserved 171.
	volatile uint32_t RSVD_172;	 // offset: 0x2f4 Reserved 172.
	volatile uint32_t RSVD_173;	 // offset: 0x2f8 Reserved 173.
	volatile uint32_t RSVD_174;	 // offset: 0x2fc Reserved 174.
	volatile uint32_t RSVD_175;	 // offset: 0x300 Reserved 175.
	volatile uint32_t RSVD_176;	 // offset: 0x304 Reserved 176.
	volatile uint32_t RSVD_177;	 // offset: 0x308 Reserved 177.
	volatile uint32_t RSVD_178;	 // offset: 0x30c Reserved 178.
	volatile uint32_t RSVD_179;	 // offset: 0x310 Reserved 179.
	volatile uint32_t RSVD_180;	 // offset: 0x314 Reserved 180.
	volatile uint32_t RSVD_181;	 // offset: 0x318 Reserved 181.
	volatile uint32_t RSVD_182;	 // offset: 0x31c Reserved 182.
	volatile uint32_t RSVD_183;	 // offset: 0x320 Reserved 183.
	volatile uint32_t RSVD_184;	 // offset: 0x324 Reserved 184.
	volatile uint32_t RSVD_185;	 // offset: 0x328 Reserved 185.
	volatile uint32_t RSVD_186;	 // offset: 0x32c Reserved 186.
	volatile uint32_t RSVD_187;	 // offset: 0x330 Reserved 187.
	volatile uint32_t RSVD_188;	 // offset: 0x334 Reserved 188.
	volatile uint32_t RSVD_189;	 // offset: 0x338 Reserved 189.
	volatile uint32_t RSVD_190;	 // offset: 0x33c Reserved 190.
	volatile uint32_t RSVD_191;	 // offset: 0x340 Reserved 191.
	volatile uint32_t RSVD_192;	 // offset: 0x344 Reserved 192.
	volatile uint32_t RSVD_193;	 // offset: 0x348 Reserved 193.
	volatile uint32_t RSVD_194;	 // offset: 0x34c Reserved 194.
	volatile uint32_t RSVD_195;	 // offset: 0x350 Reserved 195.
	volatile uint32_t RSVD_196;	 // offset: 0x354 Reserved 196.
	volatile uint32_t RSVD_197;	 // offset: 0x358 Reserved 197.
	volatile uint32_t RSVD_198;	 // offset: 0x35c Reserved 198.
	volatile uint32_t RSVD_199;	 // offset: 0x360 Reserved 199.
	volatile uint32_t RSVD_200;	 // offset: 0x364 Reserved 200.
	volatile uint32_t RSVD_201;	 // offset: 0x368 Reserved 201.
	volatile uint32_t RSVD_202;	 // offset: 0x36c Reserved 202.
	volatile uint32_t RSVD_203;	 // offset: 0x370 Reserved 203.
	volatile uint32_t RSVD_204;	 // offset: 0x374 Reserved 204.
	volatile uint32_t RSVD_205;	 // offset: 0x378 Reserved 205.
	volatile uint32_t RSVD_206;	 // offset: 0x37c Reserved 206.
	volatile uint32_t RSVD_207;	 // offset: 0x380 Reserved 207.
	volatile uint32_t RSVD_208;	 // offset: 0x384 Reserved 208.
	volatile uint32_t RSVD_209;	 // offset: 0x388 Reserved 209.
	volatile uint32_t RSVD_210;	 // offset: 0x38c Reserved 210.
	volatile uint32_t RSVD_211;	 // offset: 0x390 Reserved 211.
	volatile uint32_t RSVD_212;	 // offset: 0x394 Reserved 212.
	volatile uint32_t RSVD_213;	 // offset: 0x398 Reserved 213.
	volatile uint32_t RSVD_214;	 // offset: 0x39c Reserved 214.
	volatile uint32_t RSVD_215;	 // offset: 0x3a0 Reserved 215.
	volatile uint32_t RSVD_216;	 // offset: 0x3a4 Reserved 216.
	volatile uint32_t RSVD_217;	 // offset: 0x3a8 Reserved 217.
	volatile uint32_t RSVD_218;	 // offset: 0x3ac Reserved 218.
	volatile uint32_t RSVD_219;	 // offset: 0x3b0 Reserved 219.
	volatile uint32_t RSVD_220;	 // offset: 0x3b4 Reserved 220.
	volatile uint32_t RSVD_221;	 // offset: 0x3b8 Reserved 221.
	volatile uint32_t RSVD_222;	 // offset: 0x3bc Reserved 222.
	volatile uint32_t RSVD_223;	 // offset: 0x3c0 Reserved 223.
	volatile uint32_t RSVD_224;	 // offset: 0x3c4 Reserved 224.
	volatile uint32_t RSVD_225;	 // offset: 0x3c8 Reserved 225.
	volatile uint32_t RSVD_226;	 // offset: 0x3cc Reserved 226.
	volatile uint32_t RSVD_227;	 // offset: 0x3d0 Reserved 227.
	volatile uint32_t RSVD_228;	 // offset: 0x3d4 Reserved 228.
	volatile uint32_t RSVD_229;	 // offset: 0x3d8 Reserved 229.
	volatile uint32_t RSVD_230;	 // offset: 0x3dc Reserved 230.
	volatile uint32_t RSVD_231;	 // offset: 0x3e0 Reserved 231.
	volatile uint32_t RSVD_232;	 // offset: 0x3e4 Reserved 232.
	volatile uint32_t RSVD_233;	 // offset: 0x3e8 Reserved 233.
	volatile uint32_t RSVD_234;	 // offset: 0x3ec Reserved 234.
	volatile uint32_t RSVD_235;	 // offset: 0x3f0 Reserved 235.
	volatile uint32_t RSVD_236;	 // offset: 0x3f4 Reserved 236.
	volatile uint32_t RSVD_237;	 // offset: 0x3f8 Reserved 237.
	volatile uint32_t RSVD_238;	 // offset: 0x3fc Reserved 238.
	volatile uint32_t RSVD_239;	 // offset: 0x400 Reserved 239.
	volatile uint32_t RSVD_240;	 // offset: 0x404 Reserved 240.
	volatile uint32_t RSVD_241;	 // offset: 0x408 Reserved 241.
	volatile uint32_t RSVD_242;	 // offset: 0x40c Reserved 242.
	volatile uint32_t RSVD_243;	 // offset: 0x410 Reserved 243.
	volatile uint32_t RSVD_244;	 // offset: 0x414 Reserved 244.
	volatile uint32_t RSVD_245;	 // offset: 0x418 Reserved 245.
	volatile uint32_t RSVD_246;	 // offset: 0x41c Reserved 246.
	volatile uint32_t RSVD_247;	 // offset: 0x420 Reserved 247.
	volatile uint32_t RSVD_248;	 // offset: 0x424 Reserved 248.
	volatile uint32_t RSVD_249;	 // offset: 0x428 Reserved 249.
	volatile uint32_t RSVD_250;	 // offset: 0x42c Reserved 250.
	volatile uint32_t RSVD_251;	 // offset: 0x430 Reserved 251.
	volatile uint32_t RSVD_252;	 // offset: 0x434 Reserved 252.
	volatile uint32_t RSVD_253;	 // offset: 0x438 Reserved 253.
	volatile uint32_t RSVD_254;	 // offset: 0x43c Reserved 254.
	volatile uint32_t RSVD_255;	 // offset: 0x440 Reserved 255.
	volatile uint32_t RSVD_256;	 // offset: 0x444 Reserved 256.
	volatile uint32_t RSVD_257;	 // offset: 0x448 Reserved 257.
	volatile uint32_t RSVD_258;	 // offset: 0x44c Reserved 258.
	volatile uint32_t RSVD_259;	 // offset: 0x450 Reserved 259.
	volatile uint32_t RSVD_260;	 // offset: 0x454 Reserved 260.
	volatile uint32_t RSVD_261;	 // offset: 0x458 Reserved 261.
	volatile uint32_t RSVD_262;	 // offset: 0x45c Reserved 262.
	volatile uint32_t RSVD_263;	 // offset: 0x460 Reserved 263.
	volatile uint32_t RSVD_264;	 // offset: 0x464 Reserved 264.
	volatile uint32_t RSVD_265;	 // offset: 0x468 Reserved 265.
	volatile uint32_t RSVD_266;	 // offset: 0x46c Reserved 266.
	volatile uint32_t RSVD_267;	 // offset: 0x470 Reserved 267.
	volatile uint32_t RSVD_268;	 // offset: 0x474 Reserved 268.
	volatile uint32_t RSVD_269;	 // offset: 0x478 Reserved 269.
	volatile uint32_t RSVD_270;	 // offset: 0x47c Reserved 270.
	volatile uint32_t RSVD_271;	 // offset: 0x480 Reserved 271.
	volatile uint32_t RSVD_272;	 // offset: 0x484 Reserved 272.
	volatile uint32_t RSVD_273;	 // offset: 0x488 Reserved 273.
	volatile uint32_t RSVD_274;	 // offset: 0x48c Reserved 274.
	volatile uint32_t RSVD_275;	 // offset: 0x490 Reserved 275.
	volatile uint32_t RSVD_276;	 // offset: 0x494 Reserved 276.
	volatile uint32_t RSVD_277;	 // offset: 0x498 Reserved 277.
	volatile uint32_t RSVD_278;	 // offset: 0x49c Reserved 278.
	volatile uint32_t RSVD_279;	 // offset: 0x4a0 Reserved 279.
	volatile uint32_t RSVD_280;	 // offset: 0x4a4 Reserved 280.
	volatile uint32_t RSVD_281;	 // offset: 0x4a8 Reserved 281.
	volatile uint32_t RSVD_282;	 // offset: 0x4ac Reserved 282.
	volatile uint32_t RSVD_283;	 // offset: 0x4b0 Reserved 283.
	volatile uint32_t RSVD_284;	 // offset: 0x4b4 Reserved 284.
	volatile uint32_t RSVD_285;	 // offset: 0x4b8 Reserved 285.
	volatile uint32_t RSVD_286;	 // offset: 0x4bc Reserved 286.
	volatile uint32_t RSVD_287;	 // offset: 0x4c0 Reserved 287.
	volatile uint32_t RSVD_288;	 // offset: 0x4c4 Reserved 288.
	volatile uint32_t RSVD_289;	 // offset: 0x4c8 Reserved 289.
	volatile uint32_t RSVD_290;	 // offset: 0x4cc Reserved 290.
	volatile uint32_t RSVD_291;	 // offset: 0x4d0 Reserved 291.
	volatile uint32_t RSVD_292;	 // offset: 0x4d4 Reserved 292.
	volatile uint32_t RSVD_293;	 // offset: 0x4d8 Reserved 293.
	volatile uint32_t RSVD_294;	 // offset: 0x4dc Reserved 294.
	volatile uint32_t RSVD_295;	 // offset: 0x4e0 Reserved 295.
	volatile uint32_t RSVD_296;	 // offset: 0x4e4 Reserved 296.
	volatile uint32_t RSVD_297;	 // offset: 0x4e8 Reserved 297.
	volatile uint32_t RSVD_298;	 // offset: 0x4ec Reserved 298.
	volatile uint32_t RSVD_299;	 // offset: 0x4f0 Reserved 299.
	volatile uint32_t RSVD_300;	 // offset: 0x4f4 Reserved 300.
	volatile uint32_t RSVD_301;	 // offset: 0x4f8 Reserved 301.
	volatile uint32_t RSVD_302;	 // offset: 0x4fc Reserved 302.
	volatile uint32_t INITMR0;	 // offset: 0x500 default value: 0x510 read mask: 0x0 write mask 0xffffffff
	volatile uint32_t INITMR1;	 // offset: 0x504 default value: 0x0 read mask: 0x0 write mask 0xffffffff
	volatile uint32_t INITMR2;	 // offset: 0x508 default value: 0x0 read mask: 0x0 write mask 0xffffffff
	volatile uint32_t INITMR3;	 // offset: 0x50C default value: 0x0 read mask: 0x0 write mask 0xffffffff
	volatile uint32_t RSVD_303;	 // offset: 0x510 Reserved 303.
	volatile uint32_t RSVD_304;	 // offset: 0x514 Reserved 304.
	volatile uint32_t RSVD_305;	 // offset: 0x518 Reserved 305.
	volatile uint32_t RSVD_306;	 // offset: 0x51c Reserved 306.
	volatile uint32_t RSVD_307;	 // offset: 0x520 Reserved 307.
	volatile uint32_t RSVD_308;	 // offset: 0x524 Reserved 308.
	volatile uint32_t RSVD_309;	 // offset: 0x528 Reserved 309.
	volatile uint32_t RSVD_310;	 // offset: 0x52c Reserved 310.
	volatile uint32_t RSVD_311;	 // offset: 0x530 Reserved 311.
	volatile uint32_t RSVD_312;	 // offset: 0x534 Reserved 312.
	volatile uint32_t RSVD_313;	 // offset: 0x538 Reserved 313.
	volatile uint32_t RSVD_314;	 // offset: 0x53c Reserved 314.
	volatile uint32_t RSVD_315;	 // offset: 0x540 Reserved 315.
	volatile uint32_t RSVD_316;	 // offset: 0x544 Reserved 316.
	volatile uint32_t RSVD_317;	 // offset: 0x548 Reserved 317.
	volatile uint32_t RSVD_318;	 // offset: 0x54c Reserved 318.
	volatile uint32_t RSVD_319;	 // offset: 0x550 Reserved 319.
	volatile uint32_t RSVD_320;	 // offset: 0x554 Reserved 320.
	volatile uint32_t RSVD_321;	 // offset: 0x558 Reserved 321.
	volatile uint32_t RSVD_322;	 // offset: 0x55c Reserved 322.
	volatile uint32_t RSVD_323;	 // offset: 0x560 Reserved 323.
	volatile uint32_t RSVD_324;	 // offset: 0x564 Reserved 324.
	volatile uint32_t RSVD_325;	 // offset: 0x568 Reserved 325.
	volatile uint32_t RSVD_326;	 // offset: 0x56c Reserved 326.
	volatile uint32_t RSVD_327;	 // offset: 0x570 Reserved 327.
	volatile uint32_t RSVD_328;	 // offset: 0x574 Reserved 328.
	volatile uint32_t RSVD_329;	 // offset: 0x578 Reserved 329.
	volatile uint32_t RSVD_330;	 // offset: 0x57c Reserved 330.
	volatile uint32_t DFITMG0;	 // offset: 0x580 default value: 0x7020002 read mask: 0xe080c080 write mask 0x1f7f3f7f
	volatile uint32_t DFITMG1;	 // offset: 0x584 default value: 0x404 read mask: 0xffe0e0e0 write mask 0x1f1f1f
	volatile uint32_t DFITMG2;	 // offset: 0x588 default value: 0x202 read mask: 0xffc08080 write mask 0x3f7f7f
	volatile uint32_t RSVD_331;	 // offset: 0x58c Reserved 331.
	volatile uint32_t DFITMG4;	 // offset: 0x590 default value: 0x0 read mask: 0xff00 write mask 0xffffffff
	volatile uint32_t DFITMG5;	 // offset: 0x594 default value: 0x0 read mask: 0x0 write mask 0xffffffff
	volatile uint32_t DFITMG6;	 // offset: 0x598 default value: 0x0 read mask: 0xfffffe00 write mask 0x1ff
	volatile uint32_t RSVD_332;	 // offset: 0x59c Reserved 332.
	volatile uint32_t DFILPTMG0;	 // offset: 0x5A0 default value: 0x0 read mask: 0xffffffff write mask 0x1f1f1f
	volatile uint32_t DFILPTMG1;	 // offset: 0x5A4 default value: 0x700 read mask: 0xffffffff write mask 0x1f1f
	volatile uint32_t DFIUPDTMG0;	 // offset: 0x5A8 default value: 0x400003 read mask: 0xffffffff write mask 0x3ff03ff
	volatile uint32_t DFIUPDTMG1;	 // offset: 0x5AC default value: 0x10001 read mask: 0xffffffff write mask 0xff00ff
	volatile uint32_t DFIMSGTMG0;	 // offset: 0x5B0 default value: 0x4 read mask: 0xffffffff write mask 0xff
	volatile uint32_t DFIUPDTMG2;	 // offset: 0x5B4 default value: 0xc000012c read mask: 0xffffffff write mask 0xe0000fff
	volatile uint32_t RSVD_333;	 // offset: 0x5b8 Reserved 333.
	volatile uint32_t RSVD_334;	 // offset: 0x5bc Reserved 334.
	volatile uint32_t RSVD_335;	 // offset: 0x5c0 Reserved 335.
	volatile uint32_t RSVD_336;	 // offset: 0x5c4 Reserved 336.
	volatile uint32_t RSVD_337;	 // offset: 0x5c8 Reserved 337.
	volatile uint32_t RSVD_338;	 // offset: 0x5cc Reserved 338.
	volatile uint32_t RSVD_339;	 // offset: 0x5d0 Reserved 339.
	volatile uint32_t RSVD_340;	 // offset: 0x5d4 Reserved 340.
	volatile uint32_t RSVD_341;	 // offset: 0x5d8 Reserved 341.
	volatile uint32_t RSVD_342;	 // offset: 0x5dc Reserved 342.
	volatile uint32_t RSVD_343;	 // offset: 0x5e0 Reserved 343.
	volatile uint32_t RSVD_344;	 // offset: 0x5e4 Reserved 344.
	volatile uint32_t RSVD_345;	 // offset: 0x5e8 Reserved 345.
	volatile uint32_t RSVD_346;	 // offset: 0x5ec Reserved 346.
	volatile uint32_t RSVD_347;	 // offset: 0x5f0 Reserved 347.
	volatile uint32_t RSVD_348;	 // offset: 0x5f4 Reserved 348.
	volatile uint32_t RSVD_349;	 // offset: 0x5f8 Reserved 349.
	volatile uint32_t RSVD_350;	 // offset: 0x5fc Reserved 350.
	volatile uint32_t RFSHSET1TMG0;	 // offset: 0x600 default value: 0x2100062 read mask: 0xffffffff write mask 0xcf3f3fff
	volatile uint32_t RFSHSET1TMG1;	 // offset: 0x604 default value: 0x8c read mask: 0xffffffff write mask 0xfff0fff
	volatile uint32_t RFSHSET1TMG2;	 // offset: 0x608 default value: 0x8c8c0000 read mask: 0xffffffff write mask 0xffff0000
	volatile uint32_t RFSHSET1TMG3;	 // offset: 0x60C default value: 0x10000000 read mask: 0xffffffff write mask 0x3f000000
	volatile uint32_t RFSHSET1TMG4;	 // offset: 0x610 default value: 0x0 read mask: 0xffffffff write mask 0xfff0fff
	volatile uint32_t RSVD_351;	 // offset: 0x614 Reserved 351.
	volatile uint32_t RSVD_352;	 // offset: 0x618 Reserved 352.
	volatile uint32_t RSVD_353;	 // offset: 0x61c Reserved 353.
	volatile uint32_t RSVD_354;	 // offset: 0x620 Reserved 354.
	volatile uint32_t RSVD_355;	 // offset: 0x624 Reserved 355.
	volatile uint32_t RSVD_356;	 // offset: 0x628 Reserved 356.
	volatile uint32_t RSVD_357;	 // offset: 0x62c Reserved 357.
	volatile uint32_t RSVD_358;	 // offset: 0x630 Reserved 358.
	volatile uint32_t RSVD_359;	 // offset: 0x634 Reserved 359.
	volatile uint32_t RSVD_360;	 // offset: 0x638 Reserved 360.
	volatile uint32_t RSVD_361;	 // offset: 0x63c Reserved 361.
	volatile uint32_t RSVD_362;	 // offset: 0x640 Reserved 362.
	volatile uint32_t RSVD_363;	 // offset: 0x644 Reserved 363.
	volatile uint32_t RSVD_364;	 // offset: 0x648 Reserved 364.
	volatile uint32_t RSVD_365;	 // offset: 0x64c Reserved 365.
	volatile uint32_t RFMSET1TMG0;	 // offset: 0x650 default value: 0x8c read mask: 0xffffffff write mask 0xfff
	volatile uint32_t RSVD_366;	 // offset: 0x654 Reserved 366.
	volatile uint32_t RSVD_367;	 // offset: 0x658 Reserved 367.
	volatile uint32_t RSVD_368;	 // offset: 0x65c Reserved 368.
	volatile uint32_t RSVD_369;	 // offset: 0x660 Reserved 369.
	volatile uint32_t RSVD_370;	 // offset: 0x664 Reserved 370.
	volatile uint32_t RSVD_371;	 // offset: 0x668 Reserved 371.
	volatile uint32_t RSVD_372;	 // offset: 0x66c Reserved 372.
	volatile uint32_t RSVD_373;	 // offset: 0x670 Reserved 373.
	volatile uint32_t RSVD_374;	 // offset: 0x674 Reserved 374.
	volatile uint32_t RSVD_375;	 // offset: 0x678 Reserved 375.
	volatile uint32_t RSVD_376;	 // offset: 0x67c Reserved 376.
	volatile uint32_t RSVD_377;	 // offset: 0x680 Reserved 377.
	volatile uint32_t RSVD_378;	 // offset: 0x684 Reserved 378.
	volatile uint32_t RSVD_379;	 // offset: 0x688 Reserved 379.
	volatile uint32_t RSVD_380;	 // offset: 0x68c Reserved 380.
	volatile uint32_t RSVD_381;	 // offset: 0x690 Reserved 381.
	volatile uint32_t RSVD_382;	 // offset: 0x694 Reserved 382.
	volatile uint32_t RSVD_383;	 // offset: 0x698 Reserved 383.
	volatile uint32_t RSVD_384;	 // offset: 0x69c Reserved 384.
	volatile uint32_t RSVD_385;	 // offset: 0x6a0 Reserved 385.
	volatile uint32_t RSVD_386;	 // offset: 0x6a4 Reserved 386.
	volatile uint32_t RSVD_387;	 // offset: 0x6a8 Reserved 387.
	volatile uint32_t RSVD_388;	 // offset: 0x6ac Reserved 388.
	volatile uint32_t RSVD_389;	 // offset: 0x6b0 Reserved 389.
	volatile uint32_t RSVD_390;	 // offset: 0x6b4 Reserved 390.
	volatile uint32_t RSVD_391;	 // offset: 0x6b8 Reserved 391.
	volatile uint32_t RSVD_392;	 // offset: 0x6bc Reserved 392.
	volatile uint32_t RSVD_393;	 // offset: 0x6c0 Reserved 393.
	volatile uint32_t RSVD_394;	 // offset: 0x6c4 Reserved 394.
	volatile uint32_t RSVD_395;	 // offset: 0x6c8 Reserved 395.
	volatile uint32_t RSVD_396;	 // offset: 0x6cc Reserved 396.
	volatile uint32_t RSVD_397;	 // offset: 0x6d0 Reserved 397.
	volatile uint32_t RSVD_398;	 // offset: 0x6d4 Reserved 398.
	volatile uint32_t RSVD_399;	 // offset: 0x6d8 Reserved 399.
	volatile uint32_t RSVD_400;	 // offset: 0x6dc Reserved 400.
	volatile uint32_t RSVD_401;	 // offset: 0x6e0 Reserved 401.
	volatile uint32_t RSVD_402;	 // offset: 0x6e4 Reserved 402.
	volatile uint32_t RSVD_403;	 // offset: 0x6e8 Reserved 403.
	volatile uint32_t RSVD_404;	 // offset: 0x6ec Reserved 404.
	volatile uint32_t RSVD_405;	 // offset: 0x6f0 Reserved 405.
	volatile uint32_t RSVD_406;	 // offset: 0x6f4 Reserved 406.
	volatile uint32_t RSVD_407;	 // offset: 0x6f8 Reserved 407.
	volatile uint32_t RSVD_408;	 // offset: 0x6fc Reserved 408.
	volatile uint32_t RSVD_409;	 // offset: 0x700 Reserved 409.
	volatile uint32_t RSVD_410;	 // offset: 0x704 Reserved 410.
	volatile uint32_t RSVD_411;	 // offset: 0x708 Reserved 411.
	volatile uint32_t RSVD_412;	 // offset: 0x70c Reserved 412.
	volatile uint32_t RSVD_413;	 // offset: 0x710 Reserved 413.
	volatile uint32_t RSVD_414;	 // offset: 0x714 Reserved 414.
	volatile uint32_t RSVD_415;	 // offset: 0x718 Reserved 415.
	volatile uint32_t RSVD_416;	 // offset: 0x71c Reserved 416.
	volatile uint32_t RSVD_417;	 // offset: 0x720 Reserved 417.
	volatile uint32_t RSVD_418;	 // offset: 0x724 Reserved 418.
	volatile uint32_t RSVD_419;	 // offset: 0x728 Reserved 419.
	volatile uint32_t RSVD_420;	 // offset: 0x72c Reserved 420.
	volatile uint32_t RSVD_421;	 // offset: 0x730 Reserved 421.
	volatile uint32_t RSVD_422;	 // offset: 0x734 Reserved 422.
	volatile uint32_t RSVD_423;	 // offset: 0x738 Reserved 423.
	volatile uint32_t RSVD_424;	 // offset: 0x73c Reserved 424.
	volatile uint32_t RSVD_425;	 // offset: 0x740 Reserved 425.
	volatile uint32_t RSVD_426;	 // offset: 0x744 Reserved 426.
	volatile uint32_t RSVD_427;	 // offset: 0x748 Reserved 427.
	volatile uint32_t RSVD_428;	 // offset: 0x74c Reserved 428.
	volatile uint32_t RSVD_429;	 // offset: 0x750 Reserved 429.
	volatile uint32_t RSVD_430;	 // offset: 0x754 Reserved 430.
	volatile uint32_t RSVD_431;	 // offset: 0x758 Reserved 431.
	volatile uint32_t RSVD_432;	 // offset: 0x75c Reserved 432.
	volatile uint32_t RSVD_433;	 // offset: 0x760 Reserved 433.
	volatile uint32_t RSVD_434;	 // offset: 0x764 Reserved 434.
	volatile uint32_t RSVD_435;	 // offset: 0x768 Reserved 435.
	volatile uint32_t RSVD_436;	 // offset: 0x76c Reserved 436.
	volatile uint32_t RSVD_437;	 // offset: 0x770 Reserved 437.
	volatile uint32_t RSVD_438;	 // offset: 0x774 Reserved 438.
	volatile uint32_t RSVD_439;	 // offset: 0x778 Reserved 439.
	volatile uint32_t RSVD_440;	 // offset: 0x77c Reserved 440.
	volatile uint32_t RSVD_441;	 // offset: 0x780 Reserved 441.
	volatile uint32_t RSVD_442;	 // offset: 0x784 Reserved 442.
	volatile uint32_t RSVD_443;	 // offset: 0x788 Reserved 443.
	volatile uint32_t RSVD_444;	 // offset: 0x78c Reserved 444.
	volatile uint32_t RSVD_445;	 // offset: 0x790 Reserved 445.
	volatile uint32_t RSVD_446;	 // offset: 0x794 Reserved 446.
	volatile uint32_t RSVD_447;	 // offset: 0x798 Reserved 447.
	volatile uint32_t RSVD_448;	 // offset: 0x79c Reserved 448.
	volatile uint32_t RSVD_449;	 // offset: 0x7a0 Reserved 449.
	volatile uint32_t RSVD_450;	 // offset: 0x7a4 Reserved 450.
	volatile uint32_t RSVD_451;	 // offset: 0x7a8 Reserved 451.
	volatile uint32_t RSVD_452;	 // offset: 0x7ac Reserved 452.
	volatile uint32_t RSVD_453;	 // offset: 0x7b0 Reserved 453.
	volatile uint32_t RSVD_454;	 // offset: 0x7b4 Reserved 454.
	volatile uint32_t RSVD_455;	 // offset: 0x7b8 Reserved 455.
	volatile uint32_t RSVD_456;	 // offset: 0x7bc Reserved 456.
	volatile uint32_t RSVD_457;	 // offset: 0x7c0 Reserved 457.
	volatile uint32_t RSVD_458;	 // offset: 0x7c4 Reserved 458.
	volatile uint32_t RSVD_459;	 // offset: 0x7c8 Reserved 459.
	volatile uint32_t RSVD_460;	 // offset: 0x7cc Reserved 460.
	volatile uint32_t RSVD_461;	 // offset: 0x7d0 Reserved 461.
	volatile uint32_t RSVD_462;	 // offset: 0x7d4 Reserved 462.
	volatile uint32_t RSVD_463;	 // offset: 0x7d8 Reserved 463.
	volatile uint32_t RSVD_464;	 // offset: 0x7dc Reserved 464.
	volatile uint32_t RSVD_465;	 // offset: 0x7e0 Reserved 465.
	volatile uint32_t RSVD_466;	 // offset: 0x7e4 Reserved 466.
	volatile uint32_t RSVD_467;	 // offset: 0x7e8 Reserved 467.
	volatile uint32_t RSVD_468;	 // offset: 0x7ec Reserved 468.
	volatile uint32_t RSVD_469;	 // offset: 0x7f0 Reserved 469.
	volatile uint32_t RSVD_470;	 // offset: 0x7f4 Reserved 470.
	volatile uint32_t RSVD_471;	 // offset: 0x7f8 Reserved 471.
	volatile uint32_t RSVD_472;	 // offset: 0x7fc Reserved 472.
	volatile uint32_t ZQSET1TMG0;	 // offset: 0x800 default value: 0x400200 read mask: 0xffffffff write mask 0x3ff3fff
	volatile uint32_t ZQSET1TMG1;	 // offset: 0x804 default value: 0x2000100 read mask: 0xffffffff write mask 0x3fffffff
	volatile uint32_t RSVD_473;	 // offset: 0x808 Reserved 473.
	volatile uint32_t RSVD_474;	 // offset: 0x80c Reserved 474.
	volatile uint32_t RSVD_475;	 // offset: 0x810 Reserved 475.
	volatile uint32_t RSVD_476;	 // offset: 0x814 Reserved 476.
	volatile uint32_t RSVD_477;	 // offset: 0x818 Reserved 477.
	volatile uint32_t RSVD_478;	 // offset: 0x81c Reserved 478.
	volatile uint32_t RSVD_479;	 // offset: 0x820 Reserved 479.
	volatile uint32_t RSVD_480;	 // offset: 0x824 Reserved 480.
	volatile uint32_t RSVD_481;	 // offset: 0x828 Reserved 481.
	volatile uint32_t RSVD_482;	 // offset: 0x82c Reserved 482.
	volatile uint32_t RSVD_483;	 // offset: 0x830 Reserved 483.
	volatile uint32_t RSVD_484;	 // offset: 0x834 Reserved 484.
	volatile uint32_t RSVD_485;	 // offset: 0x838 Reserved 485.
	volatile uint32_t RSVD_486;	 // offset: 0x83c Reserved 486.
	volatile uint32_t RSVD_487;	 // offset: 0x840 Reserved 487.
	volatile uint32_t RSVD_488;	 // offset: 0x844 Reserved 488.
	volatile uint32_t RSVD_489;	 // offset: 0x848 Reserved 489.
	volatile uint32_t RSVD_490;	 // offset: 0x84c Reserved 490.
	volatile uint32_t RSVD_491;	 // offset: 0x850 Reserved 491.
	volatile uint32_t RSVD_492;	 // offset: 0x854 Reserved 492.
	volatile uint32_t RSVD_493;	 // offset: 0x858 Reserved 493.
	volatile uint32_t RSVD_494;	 // offset: 0x85c Reserved 494.
	volatile uint32_t RSVD_495;	 // offset: 0x860 Reserved 495.
	volatile uint32_t RSVD_496;	 // offset: 0x864 Reserved 496.
	volatile uint32_t RSVD_497;	 // offset: 0x868 Reserved 497.
	volatile uint32_t RSVD_498;	 // offset: 0x86c Reserved 498.
	volatile uint32_t RSVD_499;	 // offset: 0x870 Reserved 499.
	volatile uint32_t RSVD_500;	 // offset: 0x874 Reserved 500.
	volatile uint32_t RSVD_501;	 // offset: 0x878 Reserved 501.
	volatile uint32_t RSVD_502;	 // offset: 0x87c Reserved 502.
	volatile uint32_t RSVD_503;	 // offset: 0x880 Reserved 503.
	volatile uint32_t RSVD_504;	 // offset: 0x884 Reserved 504.
	volatile uint32_t RSVD_505;	 // offset: 0x888 Reserved 505.
	volatile uint32_t RSVD_506;	 // offset: 0x88c Reserved 506.
	volatile uint32_t RSVD_507;	 // offset: 0x890 Reserved 507.
	volatile uint32_t RSVD_508;	 // offset: 0x894 Reserved 508.
	volatile uint32_t RSVD_509;	 // offset: 0x898 Reserved 509.
	volatile uint32_t RSVD_510;	 // offset: 0x89c Reserved 510.
	volatile uint32_t RSVD_511;	 // offset: 0x8a0 Reserved 511.
	volatile uint32_t RSVD_512;	 // offset: 0x8a4 Reserved 512.
	volatile uint32_t RSVD_513;	 // offset: 0x8a8 Reserved 513.
	volatile uint32_t RSVD_514;	 // offset: 0x8ac Reserved 514.
	volatile uint32_t RSVD_515;	 // offset: 0x8b0 Reserved 515.
	volatile uint32_t RSVD_516;	 // offset: 0x8b4 Reserved 516.
	volatile uint32_t RSVD_517;	 // offset: 0x8b8 Reserved 517.
	volatile uint32_t RSVD_518;	 // offset: 0x8bc Reserved 518.
	volatile uint32_t RSVD_519;	 // offset: 0x8c0 Reserved 519.
	volatile uint32_t RSVD_520;	 // offset: 0x8c4 Reserved 520.
	volatile uint32_t RSVD_521;	 // offset: 0x8c8 Reserved 521.
	volatile uint32_t RSVD_522;	 // offset: 0x8cc Reserved 522.
	volatile uint32_t RSVD_523;	 // offset: 0x8d0 Reserved 523.
	volatile uint32_t RSVD_524;	 // offset: 0x8d4 Reserved 524.
	volatile uint32_t RSVD_525;	 // offset: 0x8d8 Reserved 525.
	volatile uint32_t RSVD_526;	 // offset: 0x8dc Reserved 526.
	volatile uint32_t RSVD_527;	 // offset: 0x8e0 Reserved 527.
	volatile uint32_t RSVD_528;	 // offset: 0x8e4 Reserved 528.
	volatile uint32_t RSVD_529;	 // offset: 0x8e8 Reserved 529.
	volatile uint32_t RSVD_530;	 // offset: 0x8ec Reserved 530.
	volatile uint32_t RSVD_531;	 // offset: 0x8f0 Reserved 531.
	volatile uint32_t RSVD_532;	 // offset: 0x8f4 Reserved 532.
	volatile uint32_t RSVD_533;	 // offset: 0x8f8 Reserved 533.
	volatile uint32_t RSVD_534;	 // offset: 0x8fc Reserved 534.
	volatile uint32_t RSVD_535;	 // offset: 0x900 Reserved 535.
	volatile uint32_t RSVD_536;	 // offset: 0x904 Reserved 536.
	volatile uint32_t RSVD_537;	 // offset: 0x908 Reserved 537.
	volatile uint32_t RSVD_538;	 // offset: 0x90c Reserved 538.
	volatile uint32_t RSVD_539;	 // offset: 0x910 Reserved 539.
	volatile uint32_t RSVD_540;	 // offset: 0x914 Reserved 540.
	volatile uint32_t RSVD_541;	 // offset: 0x918 Reserved 541.
	volatile uint32_t RSVD_542;	 // offset: 0x91c Reserved 542.
	volatile uint32_t RSVD_543;	 // offset: 0x920 Reserved 543.
	volatile uint32_t RSVD_544;	 // offset: 0x924 Reserved 544.
	volatile uint32_t RSVD_545;	 // offset: 0x928 Reserved 545.
	volatile uint32_t RSVD_546;	 // offset: 0x92c Reserved 546.
	volatile uint32_t RSVD_547;	 // offset: 0x930 Reserved 547.
	volatile uint32_t RSVD_548;	 // offset: 0x934 Reserved 548.
	volatile uint32_t RSVD_549;	 // offset: 0x938 Reserved 549.
	volatile uint32_t RSVD_550;	 // offset: 0x93c Reserved 550.
	volatile uint32_t RSVD_551;	 // offset: 0x940 Reserved 551.
	volatile uint32_t RSVD_552;	 // offset: 0x944 Reserved 552.
	volatile uint32_t RSVD_553;	 // offset: 0x948 Reserved 553.
	volatile uint32_t RSVD_554;	 // offset: 0x94c Reserved 554.
	volatile uint32_t RSVD_555;	 // offset: 0x950 Reserved 555.
	volatile uint32_t RSVD_556;	 // offset: 0x954 Reserved 556.
	volatile uint32_t RSVD_557;	 // offset: 0x958 Reserved 557.
	volatile uint32_t RSVD_558;	 // offset: 0x95c Reserved 558.
	volatile uint32_t RSVD_559;	 // offset: 0x960 Reserved 559.
	volatile uint32_t RSVD_560;	 // offset: 0x964 Reserved 560.
	volatile uint32_t RSVD_561;	 // offset: 0x968 Reserved 561.
	volatile uint32_t RSVD_562;	 // offset: 0x96c Reserved 562.
	volatile uint32_t RSVD_563;	 // offset: 0x970 Reserved 563.
	volatile uint32_t RSVD_564;	 // offset: 0x974 Reserved 564.
	volatile uint32_t RSVD_565;	 // offset: 0x978 Reserved 565.
	volatile uint32_t RSVD_566;	 // offset: 0x97c Reserved 566.
	volatile uint32_t RSVD_567;	 // offset: 0x980 Reserved 567.
	volatile uint32_t RSVD_568;	 // offset: 0x984 Reserved 568.
	volatile uint32_t RSVD_569;	 // offset: 0x988 Reserved 569.
	volatile uint32_t RSVD_570;	 // offset: 0x98c Reserved 570.
	volatile uint32_t RSVD_571;	 // offset: 0x990 Reserved 571.
	volatile uint32_t RSVD_572;	 // offset: 0x994 Reserved 572.
	volatile uint32_t RSVD_573;	 // offset: 0x998 Reserved 573.
	volatile uint32_t RSVD_574;	 // offset: 0x99c Reserved 574.
	volatile uint32_t RSVD_575;	 // offset: 0x9a0 Reserved 575.
	volatile uint32_t RSVD_576;	 // offset: 0x9a4 Reserved 576.
	volatile uint32_t RSVD_577;	 // offset: 0x9a8 Reserved 577.
	volatile uint32_t RSVD_578;	 // offset: 0x9ac Reserved 578.
	volatile uint32_t RSVD_579;	 // offset: 0x9b0 Reserved 579.
	volatile uint32_t RSVD_580;	 // offset: 0x9b4 Reserved 580.
	volatile uint32_t RSVD_581;	 // offset: 0x9b8 Reserved 581.
	volatile uint32_t RSVD_582;	 // offset: 0x9bc Reserved 582.
	volatile uint32_t RSVD_583;	 // offset: 0x9c0 Reserved 583.
	volatile uint32_t RSVD_584;	 // offset: 0x9c4 Reserved 584.
	volatile uint32_t RSVD_585;	 // offset: 0x9c8 Reserved 585.
	volatile uint32_t RSVD_586;	 // offset: 0x9cc Reserved 586.
	volatile uint32_t RSVD_587;	 // offset: 0x9d0 Reserved 587.
	volatile uint32_t RSVD_588;	 // offset: 0x9d4 Reserved 588.
	volatile uint32_t RSVD_589;	 // offset: 0x9d8 Reserved 589.
	volatile uint32_t RSVD_590;	 // offset: 0x9dc Reserved 590.
	volatile uint32_t RSVD_591;	 // offset: 0x9e0 Reserved 591.
	volatile uint32_t RSVD_592;	 // offset: 0x9e4 Reserved 592.
	volatile uint32_t RSVD_593;	 // offset: 0x9e8 Reserved 593.
	volatile uint32_t RSVD_594;	 // offset: 0x9ec Reserved 594.
	volatile uint32_t RSVD_595;	 // offset: 0x9f0 Reserved 595.
	volatile uint32_t RSVD_596;	 // offset: 0x9f4 Reserved 596.
	volatile uint32_t RSVD_597;	 // offset: 0x9f8 Reserved 597.
	volatile uint32_t RSVD_598;	 // offset: 0x9fc Reserved 598.
	volatile uint32_t RSVD_599;	 // offset: 0xa00 Reserved 599.
	volatile uint32_t RSVD_600;	 // offset: 0xa04 Reserved 600.
	volatile uint32_t RSVD_601;	 // offset: 0xa08 Reserved 601.
	volatile uint32_t RSVD_602;	 // offset: 0xa0c Reserved 602.
	volatile uint32_t RSVD_603;	 // offset: 0xa10 Reserved 603.
	volatile uint32_t RSVD_604;	 // offset: 0xa14 Reserved 604.
	volatile uint32_t RSVD_605;	 // offset: 0xa18 Reserved 605.
	volatile uint32_t RSVD_606;	 // offset: 0xa1c Reserved 606.
	volatile uint32_t RSVD_607;	 // offset: 0xa20 Reserved 607.
	volatile uint32_t RSVD_608;	 // offset: 0xa24 Reserved 608.
	volatile uint32_t RSVD_609;	 // offset: 0xa28 Reserved 609.
	volatile uint32_t RSVD_610;	 // offset: 0xa2c Reserved 610.
	volatile uint32_t RSVD_611;	 // offset: 0xa30 Reserved 611.
	volatile uint32_t RSVD_612;	 // offset: 0xa34 Reserved 612.
	volatile uint32_t RSVD_613;	 // offset: 0xa38 Reserved 613.
	volatile uint32_t RSVD_614;	 // offset: 0xa3c Reserved 614.
	volatile uint32_t RSVD_615;	 // offset: 0xa40 Reserved 615.
	volatile uint32_t RSVD_616;	 // offset: 0xa44 Reserved 616.
	volatile uint32_t RSVD_617;	 // offset: 0xa48 Reserved 617.
	volatile uint32_t RSVD_618;	 // offset: 0xa4c Reserved 618.
	volatile uint32_t RSVD_619;	 // offset: 0xa50 Reserved 619.
	volatile uint32_t RSVD_620;	 // offset: 0xa54 Reserved 620.
	volatile uint32_t RSVD_621;	 // offset: 0xa58 Reserved 621.
	volatile uint32_t RSVD_622;	 // offset: 0xa5c Reserved 622.
	volatile uint32_t RSVD_623;	 // offset: 0xa60 Reserved 623.
	volatile uint32_t RSVD_624;	 // offset: 0xa64 Reserved 624.
	volatile uint32_t RSVD_625;	 // offset: 0xa68 Reserved 625.
	volatile uint32_t RSVD_626;	 // offset: 0xa6c Reserved 626.
	volatile uint32_t RSVD_627;	 // offset: 0xa70 Reserved 627.
	volatile uint32_t RSVD_628;	 // offset: 0xa74 Reserved 628.
	volatile uint32_t RSVD_629;	 // offset: 0xa78 Reserved 629.
	volatile uint32_t RSVD_630;	 // offset: 0xa7c Reserved 630.
	volatile uint32_t DQSOSCCTL0;	 // offset: 0xA80 default value: 0x70 read mask: 0xffffffff write mask 0xfff5
	volatile uint32_t RSVD_631;	 // offset: 0xa84 Reserved 631.
	volatile uint32_t RSVD_632;	 // offset: 0xa88 Reserved 632.
	volatile uint32_t RSVD_633;	 // offset: 0xa8c Reserved 633.
	volatile uint32_t RSVD_634;	 // offset: 0xa90 Reserved 634.
	volatile uint32_t RSVD_635;	 // offset: 0xa94 Reserved 635.
	volatile uint32_t RSVD_636;	 // offset: 0xa98 Reserved 636.
	volatile uint32_t RSVD_637;	 // offset: 0xa9c Reserved 637.
	volatile uint32_t RSVD_638;	 // offset: 0xaa0 Reserved 638.
	volatile uint32_t RSVD_639;	 // offset: 0xaa4 Reserved 639.
	volatile uint32_t RSVD_640;	 // offset: 0xaa8 Reserved 640.
	volatile uint32_t RSVD_641;	 // offset: 0xaac Reserved 641.
	volatile uint32_t RSVD_642;	 // offset: 0xab0 Reserved 642.
	volatile uint32_t RSVD_643;	 // offset: 0xab4 Reserved 643.
	volatile uint32_t RSVD_644;	 // offset: 0xab8 Reserved 644.
	volatile uint32_t RSVD_645;	 // offset: 0xabc Reserved 645.
	volatile uint32_t RSVD_646;	 // offset: 0xac0 Reserved 646.
	volatile uint32_t RSVD_647;	 // offset: 0xac4 Reserved 647.
	volatile uint32_t RSVD_648;	 // offset: 0xac8 Reserved 648.
	volatile uint32_t RSVD_649;	 // offset: 0xacc Reserved 649.
	volatile uint32_t RSVD_650;	 // offset: 0xad0 Reserved 650.
	volatile uint32_t RSVD_651;	 // offset: 0xad4 Reserved 651.
	volatile uint32_t RSVD_652;	 // offset: 0xad8 Reserved 652.
	volatile uint32_t RSVD_653;	 // offset: 0xadc Reserved 653.
	volatile uint32_t RSVD_654;	 // offset: 0xae0 Reserved 654.
	volatile uint32_t RSVD_655;	 // offset: 0xae4 Reserved 655.
	volatile uint32_t RSVD_656;	 // offset: 0xae8 Reserved 656.
	volatile uint32_t RSVD_657;	 // offset: 0xaec Reserved 657.
	volatile uint32_t RSVD_658;	 // offset: 0xaf0 Reserved 658.
	volatile uint32_t RSVD_659;	 // offset: 0xaf4 Reserved 659.
	volatile uint32_t RSVD_660;	 // offset: 0xaf8 Reserved 660.
	volatile uint32_t RSVD_661;	 // offset: 0xafc Reserved 661.
	volatile uint32_t DERATEINT;	 // offset: 0xB00 default value: 0x800000 read mask: 0x0 write mask 0xffffffff
	volatile uint32_t DERATEVAL0;	 // offset: 0xB04 default value: 0x50f0504 read mask: 0x80c0 write mask 0xffff7f3f
	volatile uint32_t DERATEVAL1;	 // offset: 0xB08 default value: 0x514 read mask: 0xffff0000 write mask 0xffff
	volatile uint32_t RSVD_662;	 // offset: 0xb0c Reserved 662.
	volatile uint32_t RSVD_663;	 // offset: 0xb10 Reserved 663.
	volatile uint32_t RSVD_664;	 // offset: 0xb14 Reserved 664.
	volatile uint32_t RSVD_665;	 // offset: 0xb18 Reserved 665.
	volatile uint32_t RSVD_666;	 // offset: 0xb1c Reserved 666.
	volatile uint32_t RSVD_667;	 // offset: 0xb20 Reserved 667.
	volatile uint32_t RSVD_668;	 // offset: 0xb24 Reserved 668.
	volatile uint32_t RSVD_669;	 // offset: 0xb28 Reserved 669.
	volatile uint32_t RSVD_670;	 // offset: 0xb2c Reserved 670.
	volatile uint32_t RSVD_671;	 // offset: 0xb30 Reserved 671.
	volatile uint32_t RSVD_672;	 // offset: 0xb34 Reserved 672.
	volatile uint32_t RSVD_673;	 // offset: 0xb38 Reserved 673.
	volatile uint32_t RSVD_674;	 // offset: 0xb3c Reserved 674.
	volatile uint32_t RSVD_675;	 // offset: 0xb40 Reserved 675.
	volatile uint32_t RSVD_676;	 // offset: 0xb44 Reserved 676.
	volatile uint32_t RSVD_677;	 // offset: 0xb48 Reserved 677.
	volatile uint32_t RSVD_678;	 // offset: 0xb4c Reserved 678.
	volatile uint32_t RSVD_679;	 // offset: 0xb50 Reserved 679.
	volatile uint32_t RSVD_680;	 // offset: 0xb54 Reserved 680.
	volatile uint32_t RSVD_681;	 // offset: 0xb58 Reserved 681.
	volatile uint32_t RSVD_682;	 // offset: 0xb5c Reserved 682.
	volatile uint32_t RSVD_683;	 // offset: 0xb60 Reserved 683.
	volatile uint32_t RSVD_684;	 // offset: 0xb64 Reserved 684.
	volatile uint32_t RSVD_685;	 // offset: 0xb68 Reserved 685.
	volatile uint32_t RSVD_686;	 // offset: 0xb6c Reserved 686.
	volatile uint32_t RSVD_687;	 // offset: 0xb70 Reserved 687.
	volatile uint32_t RSVD_688;	 // offset: 0xb74 Reserved 688.
	volatile uint32_t RSVD_689;	 // offset: 0xb78 Reserved 689.
	volatile uint32_t RSVD_690;	 // offset: 0xb7c Reserved 690.
	volatile uint32_t HWLPTMG0;	 // offset: 0xB80 default value: 0x0 read mask: 0xf000ffff write mask 0xfff0000
	volatile uint32_t RSVD_691;	 // offset: 0xb84 Reserved 691.
	volatile uint32_t RSVD_692;	 // offset: 0xb88 Reserved 692.
	volatile uint32_t RSVD_693;	 // offset: 0xb8c Reserved 693.
	volatile uint32_t RSVD_694;	 // offset: 0xb90 Reserved 694.
	volatile uint32_t RSVD_695;	 // offset: 0xb94 Reserved 695.
	volatile uint32_t RSVD_696;	 // offset: 0xb98 Reserved 696.
	volatile uint32_t RSVD_697;	 // offset: 0xb9c Reserved 697.
	volatile uint32_t RSVD_698;	 // offset: 0xba0 Reserved 698.
	volatile uint32_t RSVD_699;	 // offset: 0xba4 Reserved 699.
	volatile uint32_t RSVD_700;	 // offset: 0xba8 Reserved 700.
	volatile uint32_t RSVD_701;	 // offset: 0xbac Reserved 701.
	volatile uint32_t RSVD_702;	 // offset: 0xbb0 Reserved 702.
	volatile uint32_t RSVD_703;	 // offset: 0xbb4 Reserved 703.
	volatile uint32_t RSVD_704;	 // offset: 0xbb8 Reserved 704.
	volatile uint32_t RSVD_705;	 // offset: 0xbbc Reserved 705.
	volatile uint32_t RSVD_706;	 // offset: 0xbc0 Reserved 706.
	volatile uint32_t RSVD_707;	 // offset: 0xbc4 Reserved 707.
	volatile uint32_t RSVD_708;	 // offset: 0xbc8 Reserved 708.
	volatile uint32_t RSVD_709;	 // offset: 0xbcc Reserved 709.
	volatile uint32_t RSVD_710;	 // offset: 0xbd0 Reserved 710.
	volatile uint32_t RSVD_711;	 // offset: 0xbd4 Reserved 711.
	volatile uint32_t RSVD_712;	 // offset: 0xbd8 Reserved 712.
	volatile uint32_t RSVD_713;	 // offset: 0xbdc Reserved 713.
	volatile uint32_t RSVD_714;	 // offset: 0xbe0 Reserved 714.
	volatile uint32_t RSVD_715;	 // offset: 0xbe4 Reserved 715.
	volatile uint32_t RSVD_716;	 // offset: 0xbe8 Reserved 716.
	volatile uint32_t RSVD_717;	 // offset: 0xbec Reserved 717.
	volatile uint32_t RSVD_718;	 // offset: 0xbf0 Reserved 718.
	volatile uint32_t RSVD_719;	 // offset: 0xbf4 Reserved 719.
	volatile uint32_t RSVD_720;	 // offset: 0xbf8 Reserved 720.
	volatile uint32_t RSVD_721;	 // offset: 0xbfc Reserved 721.
	volatile uint32_t SCHEDTMG0;	 // offset: 0xC00 default value: 0x0 read mask: 0xffffffff write mask 0x7fff
	volatile uint32_t RSVD_722;	 // offset: 0xc04 Reserved 722.
	volatile uint32_t RSVD_723;	 // offset: 0xc08 Reserved 723.
	volatile uint32_t RSVD_724;	 // offset: 0xc0c Reserved 724.
	volatile uint32_t RSVD_725;	 // offset: 0xc10 Reserved 725.
	volatile uint32_t RSVD_726;	 // offset: 0xc14 Reserved 726.
	volatile uint32_t RSVD_727;	 // offset: 0xc18 Reserved 727.
	volatile uint32_t RSVD_728;	 // offset: 0xc1c Reserved 728.
	volatile uint32_t RSVD_729;	 // offset: 0xc20 Reserved 729.
	volatile uint32_t RSVD_730;	 // offset: 0xc24 Reserved 730.
	volatile uint32_t RSVD_731;	 // offset: 0xc28 Reserved 731.
	volatile uint32_t RSVD_732;	 // offset: 0xc2c Reserved 732.
	volatile uint32_t RSVD_733;	 // offset: 0xc30 Reserved 733.
	volatile uint32_t RSVD_734;	 // offset: 0xc34 Reserved 734.
	volatile uint32_t RSVD_735;	 // offset: 0xc38 Reserved 735.
	volatile uint32_t RSVD_736;	 // offset: 0xc3c Reserved 736.
	volatile uint32_t RSVD_737;	 // offset: 0xc40 Reserved 737.
	volatile uint32_t RSVD_738;	 // offset: 0xc44 Reserved 738.
	volatile uint32_t RSVD_739;	 // offset: 0xc48 Reserved 739.
	volatile uint32_t RSVD_740;	 // offset: 0xc4c Reserved 740.
	volatile uint32_t RSVD_741;	 // offset: 0xc50 Reserved 741.
	volatile uint32_t RSVD_742;	 // offset: 0xc54 Reserved 742.
	volatile uint32_t RSVD_743;	 // offset: 0xc58 Reserved 743.
	volatile uint32_t RSVD_744;	 // offset: 0xc5c Reserved 744.
	volatile uint32_t RSVD_745;	 // offset: 0xc60 Reserved 745.
	volatile uint32_t RSVD_746;	 // offset: 0xc64 Reserved 746.
	volatile uint32_t RSVD_747;	 // offset: 0xc68 Reserved 747.
	volatile uint32_t RSVD_748;	 // offset: 0xc6c Reserved 748.
	volatile uint32_t RSVD_749;	 // offset: 0xc70 Reserved 749.
	volatile uint32_t RSVD_750;	 // offset: 0xc74 Reserved 750.
	volatile uint32_t RSVD_751;	 // offset: 0xc78 Reserved 751.
	volatile uint32_t RSVD_752;	 // offset: 0xc7c Reserved 752.
	volatile uint32_t PERFHPR1;	 // offset: 0xC80 default value: 0xf000001 read mask: 0xff0000 write mask 0xff00ffff
	volatile uint32_t PERFLPR1;	 // offset: 0xC84 default value: 0xf00007f read mask: 0xff0000 write mask 0xff00ffff
	volatile uint32_t PERFWR1;	 // offset: 0xC88 default value: 0xf00007f read mask: 0xff0000 write mask 0xff00ffff
	volatile uint32_t RSVD_753;	 // offset: 0xc8c Reserved 753.
	volatile uint32_t RSVD_754;	 // offset: 0xc90 Reserved 754.
	volatile uint32_t RSVD_755;	 // offset: 0xc94 Reserved 755.
	volatile uint32_t RSVD_756;	 // offset: 0xc98 Reserved 756.
	volatile uint32_t RSVD_757;	 // offset: 0xc9c Reserved 757.
	volatile uint32_t RSVD_758;	 // offset: 0xca0 Reserved 758.
	volatile uint32_t RSVD_759;	 // offset: 0xca4 Reserved 759.
	volatile uint32_t RSVD_760;	 // offset: 0xca8 Reserved 760.
	volatile uint32_t RSVD_761;	 // offset: 0xcac Reserved 761.
	volatile uint32_t RSVD_762;	 // offset: 0xcb0 Reserved 762.
	volatile uint32_t RSVD_763;	 // offset: 0xcb4 Reserved 763.
	volatile uint32_t RSVD_764;	 // offset: 0xcb8 Reserved 764.
	volatile uint32_t RSVD_765;	 // offset: 0xcbc Reserved 765.
	volatile uint32_t RSVD_766;	 // offset: 0xcc0 Reserved 766.
	volatile uint32_t RSVD_767;	 // offset: 0xcc4 Reserved 767.
	volatile uint32_t RSVD_768;	 // offset: 0xcc8 Reserved 768.
	volatile uint32_t RSVD_769;	 // offset: 0xccc Reserved 769.
	volatile uint32_t RSVD_770;	 // offset: 0xcd0 Reserved 770.
	volatile uint32_t RSVD_771;	 // offset: 0xcd4 Reserved 771.
	volatile uint32_t RSVD_772;	 // offset: 0xcd8 Reserved 772.
	volatile uint32_t RSVD_773;	 // offset: 0xcdc Reserved 773.
	volatile uint32_t RSVD_774;	 // offset: 0xce0 Reserved 774.
	volatile uint32_t RSVD_775;	 // offset: 0xce4 Reserved 775.
	volatile uint32_t RSVD_776;	 // offset: 0xce8 Reserved 776.
	volatile uint32_t RSVD_777;	 // offset: 0xcec Reserved 777.
	volatile uint32_t RSVD_778;	 // offset: 0xcf0 Reserved 778.
	volatile uint32_t RSVD_779;	 // offset: 0xcf4 Reserved 779.
	volatile uint32_t RSVD_780;	 // offset: 0xcf8 Reserved 780.
	volatile uint32_t RSVD_781;	 // offset: 0xcfc Reserved 781.
	volatile uint32_t TMGCFG;	 // offset: 0xD00 default value: 0x0 read mask: 0xffffffff write mask 0x1
	volatile uint32_t RANKTMG0;	 // offset: 0xD04 default value: 0x606 read mask: 0xffff0000 write mask 0xffff
	volatile uint32_t RANKTMG1;	 // offset: 0xD08 default value: 0xf0f read mask: 0xffff0000 write mask 0xffff
	volatile uint32_t PWRTMG;	 // offset: 0xD0C default value: 0x400010 read mask: 0xfc00ff80 write mask 0x3ff007f
	volatile uint32_t RSVD_782;	 // offset: 0xd10 Reserved 782.
	volatile uint32_t RSVD_783;	 // offset: 0xd14 Reserved 783.
	volatile uint32_t RSVD_784;	 // offset: 0xd18 Reserved 784.
	volatile uint32_t RSVD_785;	 // offset: 0xd1c Reserved 785.
	volatile uint32_t RSVD_786;	 // offset: 0xd20 Reserved 786.
	volatile uint32_t RSVD_787;	 // offset: 0xd24 Reserved 787.
	volatile uint32_t RSVD_788;	 // offset: 0xd28 Reserved 788.
	volatile uint32_t RSVD_789;	 // offset: 0xd2c Reserved 789.
	volatile uint32_t RSVD_790;	 // offset: 0xd30 Reserved 790.
	volatile uint32_t RSVD_791;	 // offset: 0xd34 Reserved 791.
	volatile uint32_t RSVD_792;	 // offset: 0xd38 Reserved 792.
	volatile uint32_t RSVD_793;	 // offset: 0xd3c Reserved 793.
	volatile uint32_t RSVD_794;	 // offset: 0xd40 Reserved 794.
	volatile uint32_t RSVD_795;	 // offset: 0xd44 Reserved 795.
	volatile uint32_t RSVD_796;	 // offset: 0xd48 Reserved 796.
	volatile uint32_t RSVD_797;	 // offset: 0xd4c Reserved 797.
	volatile uint32_t RSVD_798;	 // offset: 0xd50 Reserved 798.
	volatile uint32_t RSVD_799;	 // offset: 0xd54 Reserved 799.
	volatile uint32_t RSVD_800;	 // offset: 0xd58 Reserved 800.
	volatile uint32_t RSVD_801;	 // offset: 0xd5c Reserved 801.
	volatile uint32_t RSVD_802;	 // offset: 0xd60 Reserved 802.
	volatile uint32_t RSVD_803;	 // offset: 0xd64 Reserved 803.
	volatile uint32_t RSVD_804;	 // offset: 0xd68 Reserved 804.
	volatile uint32_t RSVD_805;	 // offset: 0xd6c Reserved 805.
	volatile uint32_t RSVD_806;	 // offset: 0xd70 Reserved 806.
	volatile uint32_t RSVD_807;	 // offset: 0xd74 Reserved 807.
	volatile uint32_t RSVD_808;	 // offset: 0xd78 Reserved 808.
	volatile uint32_t RSVD_809;	 // offset: 0xd7c Reserved 809.
	volatile uint32_t LNKECCCTL0;	 // offset: 0xD80 default value: 0x0 read mask: 0xfffffffc write mask 0x3
} LPDDR5_REGB_FREQ0_CH0_t;

/****************************** Bit definition for DRAMSET1TMG0 register ********************************/

#define DRAMSET1TMG0_T_RAS_MIN_Pos		(0U)
#define DRAMSET1TMG0_T_RAS_MIN_Msk		(0xffUL << DRAMSET1TMG0_T_RAS_MIN_Pos)
#define DRAMSET1TMG0_T_RAS_MIN    		DRAMSET1TMG0_T_RAS_MIN_Msk


#define DRAMSET1TMG0_T_RAS_MAX_Pos		(8U)
#define DRAMSET1TMG0_T_RAS_MAX_Msk		(0xffUL << DRAMSET1TMG0_T_RAS_MAX_Pos)
#define DRAMSET1TMG0_T_RAS_MAX    		DRAMSET1TMG0_T_RAS_MAX_Msk


#define DRAMSET1TMG0_T_FAW_Pos		(16U)
#define DRAMSET1TMG0_T_FAW_Msk		(0xffUL << DRAMSET1TMG0_T_FAW_Pos)
#define DRAMSET1TMG0_T_FAW    		DRAMSET1TMG0_T_FAW_Msk


#define DRAMSET1TMG0_WR2PRE_Pos		(24U)
#define DRAMSET1TMG0_WR2PRE_Msk		(0xffUL << DRAMSET1TMG0_WR2PRE_Pos)
#define DRAMSET1TMG0_WR2PRE    		DRAMSET1TMG0_WR2PRE_Msk


/****************************** Bit definition for DRAMSET1TMG1 register ********************************/

#define DRAMSET1TMG1_T_RC_Pos		(0U)
#define DRAMSET1TMG1_T_RC_Msk		(0xffUL << DRAMSET1TMG1_T_RC_Pos)
#define DRAMSET1TMG1_T_RC    		DRAMSET1TMG1_T_RC_Msk


#define DRAMSET1TMG1_RD2PRE_Pos		(8U)
#define DRAMSET1TMG1_RD2PRE_Msk		(0xffUL << DRAMSET1TMG1_RD2PRE_Pos)
#define DRAMSET1TMG1_RD2PRE    		DRAMSET1TMG1_RD2PRE_Msk


#define DRAMSET1TMG1_T_XP_Pos		(16U)
#define DRAMSET1TMG1_T_XP_Msk		(0x3fUL << DRAMSET1TMG1_T_XP_Pos)
#define DRAMSET1TMG1_T_XP    		DRAMSET1TMG1_T_XP_Msk


#define DRAMSET1TMG1_T_RCD_WRITE_Pos		(24U)
#define DRAMSET1TMG1_T_RCD_WRITE_Msk		(0xffUL << DRAMSET1TMG1_T_RCD_WRITE_Pos)
#define DRAMSET1TMG1_T_RCD_WRITE    		DRAMSET1TMG1_T_RCD_WRITE_Msk


/****************************** Bit definition for DRAMSET1TMG2 register ********************************/

#define DRAMSET1TMG2_WR2RD_Pos		(0U)
#define DRAMSET1TMG2_WR2RD_Msk		(0xffUL << DRAMSET1TMG2_WR2RD_Pos)
#define DRAMSET1TMG2_WR2RD    		DRAMSET1TMG2_WR2RD_Msk


#define DRAMSET1TMG2_RD2WR_Pos		(8U)
#define DRAMSET1TMG2_RD2WR_Msk		(0xffUL << DRAMSET1TMG2_RD2WR_Pos)
#define DRAMSET1TMG2_RD2WR    		DRAMSET1TMG2_RD2WR_Msk


#define DRAMSET1TMG2_READ_LATENCY_Pos		(16U)
#define DRAMSET1TMG2_READ_LATENCY_Msk		(0x7fUL << DRAMSET1TMG2_READ_LATENCY_Pos)
#define DRAMSET1TMG2_READ_LATENCY    		DRAMSET1TMG2_READ_LATENCY_Msk


#define DRAMSET1TMG2_WRITE_LATENCY_Pos		(24U)
#define DRAMSET1TMG2_WRITE_LATENCY_Msk		(0x7fUL << DRAMSET1TMG2_WRITE_LATENCY_Pos)
#define DRAMSET1TMG2_WRITE_LATENCY    		DRAMSET1TMG2_WRITE_LATENCY_Msk


/****************************** Bit definition for DRAMSET1TMG3 register ********************************/

#define DRAMSET1TMG3_WR2MR_Pos		(0U)
#define DRAMSET1TMG3_WR2MR_Msk		(0xffUL << DRAMSET1TMG3_WR2MR_Pos)
#define DRAMSET1TMG3_WR2MR    		DRAMSET1TMG3_WR2MR_Msk


#define DRAMSET1TMG3_RD2MR_Pos		(8U)
#define DRAMSET1TMG3_RD2MR_Msk		(0xffUL << DRAMSET1TMG3_RD2MR_Pos)
#define DRAMSET1TMG3_RD2MR    		DRAMSET1TMG3_RD2MR_Msk


#define DRAMSET1TMG3_T_MR_Pos		(16U)
#define DRAMSET1TMG3_T_MR_Msk		(0x7fUL << DRAMSET1TMG3_T_MR_Pos)
#define DRAMSET1TMG3_T_MR    		DRAMSET1TMG3_T_MR_Msk


/****************************** Bit definition for DRAMSET1TMG4 register ********************************/

#define DRAMSET1TMG4_T_RP_Pos		(0U)
#define DRAMSET1TMG4_T_RP_Msk		(0x7fUL << DRAMSET1TMG4_T_RP_Pos)
#define DRAMSET1TMG4_T_RP    		DRAMSET1TMG4_T_RP_Msk


#define DRAMSET1TMG4_T_RRD_Pos		(8U)
#define DRAMSET1TMG4_T_RRD_Msk		(0x3fUL << DRAMSET1TMG4_T_RRD_Pos)
#define DRAMSET1TMG4_T_RRD    		DRAMSET1TMG4_T_RRD_Msk


#define DRAMSET1TMG4_T_CCD_Pos		(16U)
#define DRAMSET1TMG4_T_CCD_Msk		(0x3fUL << DRAMSET1TMG4_T_CCD_Pos)
#define DRAMSET1TMG4_T_CCD    		DRAMSET1TMG4_T_CCD_Msk


#define DRAMSET1TMG4_T_RCD_Pos		(24U)
#define DRAMSET1TMG4_T_RCD_Msk		(0xffUL << DRAMSET1TMG4_T_RCD_Pos)
#define DRAMSET1TMG4_T_RCD    		DRAMSET1TMG4_T_RCD_Msk


/****************************** Bit definition for DRAMSET1TMG5 register ********************************/

#define DRAMSET1TMG5_T_CKE_Pos		(0U)
#define DRAMSET1TMG5_T_CKE_Msk		(0x3fUL << DRAMSET1TMG5_T_CKE_Pos)
#define DRAMSET1TMG5_T_CKE    		DRAMSET1TMG5_T_CKE_Msk


#define DRAMSET1TMG5_T_CKESR_Pos		(8U)
#define DRAMSET1TMG5_T_CKESR_Msk		(0x7fUL << DRAMSET1TMG5_T_CKESR_Pos)
#define DRAMSET1TMG5_T_CKESR    		DRAMSET1TMG5_T_CKESR_Msk


#define DRAMSET1TMG5_T_CKSRE_Pos		(16U)
#define DRAMSET1TMG5_T_CKSRE_Msk		(0x7fUL << DRAMSET1TMG5_T_CKSRE_Pos)
#define DRAMSET1TMG5_T_CKSRE    		DRAMSET1TMG5_T_CKSRE_Msk


#define DRAMSET1TMG5_T_CKSRX_Pos		(24U)
#define DRAMSET1TMG5_T_CKSRX_Msk		(0x3fUL << DRAMSET1TMG5_T_CKSRX_Pos)
#define DRAMSET1TMG5_T_CKSRX    		DRAMSET1TMG5_T_CKSRX_Msk


/****************************** Bit definition for DRAMSET1TMG6 register ********************************/

#define DRAMSET1TMG6_T_CKCSX_Pos		(0U)
#define DRAMSET1TMG6_T_CKCSX_Msk		(0x3fUL << DRAMSET1TMG6_T_CKCSX_Pos)
#define DRAMSET1TMG6_T_CKCSX    		DRAMSET1TMG6_T_CKCSX_Msk


/****************************** Bit definition for DRAMSET1TMG7 register ********************************/

#define DRAMSET1TMG7_T_CSH_Pos		(0U)
#define DRAMSET1TMG7_T_CSH_Msk		(0xfUL << DRAMSET1TMG7_T_CSH_Pos)
#define DRAMSET1TMG7_T_CSH    		DRAMSET1TMG7_T_CSH_Msk


/****************************** Bit definition for DRAMSET1TMG9 register ********************************/

#define DRAMSET1TMG9_WR2RD_S_Pos		(0U)
#define DRAMSET1TMG9_WR2RD_S_Msk		(0xffUL << DRAMSET1TMG9_WR2RD_S_Pos)
#define DRAMSET1TMG9_WR2RD_S    		DRAMSET1TMG9_WR2RD_S_Msk


#define DRAMSET1TMG9_T_RRD_S_Pos		(8U)
#define DRAMSET1TMG9_T_RRD_S_Msk		(0x3fUL << DRAMSET1TMG9_T_RRD_S_Pos)
#define DRAMSET1TMG9_T_RRD_S    		DRAMSET1TMG9_T_RRD_S_Msk


#define DRAMSET1TMG9_T_CCD_S_Pos		(16U)
#define DRAMSET1TMG9_T_CCD_S_Msk		(0x1fUL << DRAMSET1TMG9_T_CCD_S_Pos)
#define DRAMSET1TMG9_T_CCD_S    		DRAMSET1TMG9_T_CCD_S_Msk


/****************************** Bit definition for DRAMSET1TMG12 register ********************************/

#define DRAMSET1TMG12_T_CMDCKE_Pos		(16U)
#define DRAMSET1TMG12_T_CMDCKE_Msk		(0xfUL << DRAMSET1TMG12_T_CMDCKE_Pos)
#define DRAMSET1TMG12_T_CMDCKE    		DRAMSET1TMG12_T_CMDCKE_Msk


/****************************** Bit definition for DRAMSET1TMG13 register ********************************/

#define DRAMSET1TMG13_T_PPD_Pos		(0U)
#define DRAMSET1TMG13_T_PPD_Msk		(0xfUL << DRAMSET1TMG13_T_PPD_Pos)
#define DRAMSET1TMG13_T_PPD    		DRAMSET1TMG13_T_PPD_Msk


#define DRAMSET1TMG13_T_CCD_MW_Pos		(16U)
#define DRAMSET1TMG13_T_CCD_MW_Msk		(0x7fUL << DRAMSET1TMG13_T_CCD_MW_Pos)
#define DRAMSET1TMG13_T_CCD_MW    		DRAMSET1TMG13_T_CCD_MW_Msk


#define DRAMSET1TMG13_ODTLOFF_Pos		(24U)
#define DRAMSET1TMG13_ODTLOFF_Msk		(0x7fUL << DRAMSET1TMG13_ODTLOFF_Pos)
#define DRAMSET1TMG13_ODTLOFF    		DRAMSET1TMG13_ODTLOFF_Msk


/****************************** Bit definition for DRAMSET1TMG14 register ********************************/

#define DRAMSET1TMG14_T_XSR_Pos		(0U)
#define DRAMSET1TMG14_T_XSR_Msk		(0xfffUL << DRAMSET1TMG14_T_XSR_Pos)
#define DRAMSET1TMG14_T_XSR    		DRAMSET1TMG14_T_XSR_Msk


#define DRAMSET1TMG14_T_OSCO_Pos		(16U)
#define DRAMSET1TMG14_T_OSCO_Msk		(0x1ffUL << DRAMSET1TMG14_T_OSCO_Pos)
#define DRAMSET1TMG14_T_OSCO    		DRAMSET1TMG14_T_OSCO_Msk


/****************************** Bit definition for DRAMSET1TMG23 register ********************************/

#define DRAMSET1TMG23_T_PDN_Pos		(0U)
#define DRAMSET1TMG23_T_PDN_Msk		(0xfffUL << DRAMSET1TMG23_T_PDN_Pos)
#define DRAMSET1TMG23_T_PDN    		DRAMSET1TMG23_T_PDN_Msk


#define DRAMSET1TMG23_T_XSR_DSM_X1024_Pos		(16U)
#define DRAMSET1TMG23_T_XSR_DSM_X1024_Msk		(0xffUL << DRAMSET1TMG23_T_XSR_DSM_X1024_Pos)
#define DRAMSET1TMG23_T_XSR_DSM_X1024    		DRAMSET1TMG23_T_XSR_DSM_X1024_Msk


/****************************** Bit definition for DRAMSET1TMG24 register ********************************/

#define DRAMSET1TMG24_MAX_WR_SYNC_Pos		(0U)
#define DRAMSET1TMG24_MAX_WR_SYNC_Msk		(0xffUL << DRAMSET1TMG24_MAX_WR_SYNC_Pos)
#define DRAMSET1TMG24_MAX_WR_SYNC    		DRAMSET1TMG24_MAX_WR_SYNC_Msk


#define DRAMSET1TMG24_MAX_RD_SYNC_Pos		(8U)
#define DRAMSET1TMG24_MAX_RD_SYNC_Msk		(0xffUL << DRAMSET1TMG24_MAX_RD_SYNC_Pos)
#define DRAMSET1TMG24_MAX_RD_SYNC    		DRAMSET1TMG24_MAX_RD_SYNC_Msk


#define DRAMSET1TMG24_RD2WR_S_Pos		(16U)
#define DRAMSET1TMG24_RD2WR_S_Msk		(0xffUL << DRAMSET1TMG24_RD2WR_S_Pos)
#define DRAMSET1TMG24_RD2WR_S    		DRAMSET1TMG24_RD2WR_S_Msk


#define DRAMSET1TMG24_BANK_ORG_Pos		(24U)
#define DRAMSET1TMG24_BANK_ORG_Msk		(0x3UL << DRAMSET1TMG24_BANK_ORG_Pos)
#define DRAMSET1TMG24_BANK_ORG    		DRAMSET1TMG24_BANK_ORG_Msk


/****************************** Bit definition for DRAMSET1TMG25 register ********************************/

#define DRAMSET1TMG25_RDA2PRE_Pos		(0U)
#define DRAMSET1TMG25_RDA2PRE_Msk		(0xffUL << DRAMSET1TMG25_RDA2PRE_Pos)
#define DRAMSET1TMG25_RDA2PRE    		DRAMSET1TMG25_RDA2PRE_Msk


#define DRAMSET1TMG25_WRA2PRE_Pos		(8U)
#define DRAMSET1TMG25_WRA2PRE_Msk		(0xffUL << DRAMSET1TMG25_WRA2PRE_Pos)
#define DRAMSET1TMG25_WRA2PRE    		DRAMSET1TMG25_WRA2PRE_Msk


#define DRAMSET1TMG25_LPDDR4_DIFF_BANK_RWA2PRE_Pos		(16U)
#define DRAMSET1TMG25_LPDDR4_DIFF_BANK_RWA2PRE_Msk		(0x7UL << DRAMSET1TMG25_LPDDR4_DIFF_BANK_RWA2PRE_Pos)
#define DRAMSET1TMG25_LPDDR4_DIFF_BANK_RWA2PRE    		DRAMSET1TMG25_LPDDR4_DIFF_BANK_RWA2PRE_Msk


/****************************** Bit definition for DRAMSET1TMG30 register ********************************/

#define DRAMSET1TMG30_MRR2RD_Pos		(0U)
#define DRAMSET1TMG30_MRR2RD_Msk		(0xffUL << DRAMSET1TMG30_MRR2RD_Pos)
#define DRAMSET1TMG30_MRR2RD    		DRAMSET1TMG30_MRR2RD_Msk


#define DRAMSET1TMG30_MRR2WR_Pos		(8U)
#define DRAMSET1TMG30_MRR2WR_Msk		(0xffUL << DRAMSET1TMG30_MRR2WR_Pos)
#define DRAMSET1TMG30_MRR2WR    		DRAMSET1TMG30_MRR2WR_Msk


#define DRAMSET1TMG30_MRR2MRW_Pos		(16U)
#define DRAMSET1TMG30_MRR2MRW_Msk		(0xffUL << DRAMSET1TMG30_MRR2MRW_Pos)
#define DRAMSET1TMG30_MRR2MRW    		DRAMSET1TMG30_MRR2MRW_Msk


/****************************** Bit definition for DRAMSET1TMG32 register ********************************/

#define DRAMSET1TMG32_WS_FS2WCK_SUS_Pos		(0U)
#define DRAMSET1TMG32_WS_FS2WCK_SUS_Msk		(0xfUL << DRAMSET1TMG32_WS_FS2WCK_SUS_Pos)
#define DRAMSET1TMG32_WS_FS2WCK_SUS    		DRAMSET1TMG32_WS_FS2WCK_SUS_Msk


#define DRAMSET1TMG32_T_WCKSUS_Pos		(8U)
#define DRAMSET1TMG32_T_WCKSUS_Msk		(0xfUL << DRAMSET1TMG32_T_WCKSUS_Pos)
#define DRAMSET1TMG32_T_WCKSUS    		DRAMSET1TMG32_T_WCKSUS_Msk


#define DRAMSET1TMG32_WS_OFF2WS_FS_Pos		(16U)
#define DRAMSET1TMG32_WS_OFF2WS_FS_Msk		(0xfUL << DRAMSET1TMG32_WS_OFF2WS_FS_Pos)
#define DRAMSET1TMG32_WS_OFF2WS_FS    		DRAMSET1TMG32_WS_OFF2WS_FS_Msk


/****************************** Bit definition for INITMR0 register ********************************/

#define INITMR0_EMR_Pos		(0U)
#define INITMR0_EMR_Msk		(0xffffUL << INITMR0_EMR_Pos)
#define INITMR0_EMR    		INITMR0_EMR_Msk


#define INITMR0_MR_Pos		(16U)
#define INITMR0_MR_Msk		(0xffffUL << INITMR0_MR_Pos)
#define INITMR0_MR    		INITMR0_MR_Msk


/****************************** Bit definition for INITMR1 register ********************************/

#define INITMR1_EMR3_Pos		(0U)
#define INITMR1_EMR3_Msk		(0xffffUL << INITMR1_EMR3_Pos)
#define INITMR1_EMR3    		INITMR1_EMR3_Msk


#define INITMR1_EMR2_Pos		(16U)
#define INITMR1_EMR2_Msk		(0xffffUL << INITMR1_EMR2_Pos)
#define INITMR1_EMR2    		INITMR1_EMR2_Msk


/****************************** Bit definition for INITMR2 register ********************************/

#define INITMR2_MR5_Pos		(0U)
#define INITMR2_MR5_Msk		(0xffffUL << INITMR2_MR5_Pos)
#define INITMR2_MR5    		INITMR2_MR5_Msk


#define INITMR2_MR4_Pos		(16U)
#define INITMR2_MR4_Msk		(0xffffUL << INITMR2_MR4_Pos)
#define INITMR2_MR4    		INITMR2_MR4_Msk


/****************************** Bit definition for INITMR3 register ********************************/

#define INITMR3_MR6_Pos		(0U)
#define INITMR3_MR6_Msk		(0xffffUL << INITMR3_MR6_Pos)
#define INITMR3_MR6    		INITMR3_MR6_Msk


#define INITMR3_MR22_Pos		(16U)
#define INITMR3_MR22_Msk		(0xffffUL << INITMR3_MR22_Pos)
#define INITMR3_MR22    		INITMR3_MR22_Msk


/****************************** Bit definition for DFITMG0 register ********************************/

#define DFITMG0_DFI_TPHY_WRLAT_Pos		(0U)
#define DFITMG0_DFI_TPHY_WRLAT_Msk		(0x7fUL << DFITMG0_DFI_TPHY_WRLAT_Pos)
#define DFITMG0_DFI_TPHY_WRLAT    		DFITMG0_DFI_TPHY_WRLAT_Msk


#define DFITMG0_DFI_TPHY_WRDATA_Pos		(8U)
#define DFITMG0_DFI_TPHY_WRDATA_Msk		(0x3fUL << DFITMG0_DFI_TPHY_WRDATA_Pos)
#define DFITMG0_DFI_TPHY_WRDATA    		DFITMG0_DFI_TPHY_WRDATA_Msk


#define DFITMG0_DFI_T_RDDATA_EN_Pos		(16U)
#define DFITMG0_DFI_T_RDDATA_EN_Msk		(0x7fUL << DFITMG0_DFI_T_RDDATA_EN_Pos)
#define DFITMG0_DFI_T_RDDATA_EN    		DFITMG0_DFI_T_RDDATA_EN_Msk


#define DFITMG0_DFI_T_CTRL_DELAY_Pos		(24U)
#define DFITMG0_DFI_T_CTRL_DELAY_Msk		(0x1fUL << DFITMG0_DFI_T_CTRL_DELAY_Pos)
#define DFITMG0_DFI_T_CTRL_DELAY    		DFITMG0_DFI_T_CTRL_DELAY_Msk


/****************************** Bit definition for DFITMG1 register ********************************/

#define DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos		(0U)
#define DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk		(0x1fUL << DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos)
#define DFITMG1_DFI_T_DRAM_CLK_ENABLE    		DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk


#define DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos		(8U)
#define DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk		(0x1fUL << DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos)
#define DFITMG1_DFI_T_DRAM_CLK_DISABLE    		DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk


#define DFITMG1_DFI_T_WRDATA_DELAY_Pos		(16U)
#define DFITMG1_DFI_T_WRDATA_DELAY_Msk		(0x1fUL << DFITMG1_DFI_T_WRDATA_DELAY_Pos)
#define DFITMG1_DFI_T_WRDATA_DELAY    		DFITMG1_DFI_T_WRDATA_DELAY_Msk


/****************************** Bit definition for DFITMG2 register ********************************/

#define DFITMG2_DFI_TPHY_WRCSLAT_Pos		(0U)
#define DFITMG2_DFI_TPHY_WRCSLAT_Msk		(0x7fUL << DFITMG2_DFI_TPHY_WRCSLAT_Pos)
#define DFITMG2_DFI_TPHY_WRCSLAT    		DFITMG2_DFI_TPHY_WRCSLAT_Msk


#define DFITMG2_DFI_TPHY_RDCSLAT_Pos		(8U)
#define DFITMG2_DFI_TPHY_RDCSLAT_Msk		(0x7fUL << DFITMG2_DFI_TPHY_RDCSLAT_Pos)
#define DFITMG2_DFI_TPHY_RDCSLAT    		DFITMG2_DFI_TPHY_RDCSLAT_Msk


#define DFITMG2_DFI_TWCK_DELAY_Pos		(16U)
#define DFITMG2_DFI_TWCK_DELAY_Msk		(0x3fUL << DFITMG2_DFI_TWCK_DELAY_Pos)
#define DFITMG2_DFI_TWCK_DELAY    		DFITMG2_DFI_TWCK_DELAY_Msk


/****************************** Bit definition for DFITMG4 register ********************************/

#define DFITMG4_DFI_TWCK_DIS_Pos		(0U)
#define DFITMG4_DFI_TWCK_DIS_Msk		(0xffUL << DFITMG4_DFI_TWCK_DIS_Pos)
#define DFITMG4_DFI_TWCK_DIS    		DFITMG4_DFI_TWCK_DIS_Msk


#define DFITMG4_DFI_TWCK_EN_FS_Pos		(8U)
#define DFITMG4_DFI_TWCK_EN_FS_Msk		(0xffUL << DFITMG4_DFI_TWCK_EN_FS_Pos)
#define DFITMG4_DFI_TWCK_EN_FS    		DFITMG4_DFI_TWCK_EN_FS_Msk


#define DFITMG4_DFI_TWCK_EN_WR_Pos		(16U)
#define DFITMG4_DFI_TWCK_EN_WR_Msk		(0xffUL << DFITMG4_DFI_TWCK_EN_WR_Pos)
#define DFITMG4_DFI_TWCK_EN_WR    		DFITMG4_DFI_TWCK_EN_WR_Msk


#define DFITMG4_DFI_TWCK_EN_RD_Pos		(24U)
#define DFITMG4_DFI_TWCK_EN_RD_Msk		(0xffUL << DFITMG4_DFI_TWCK_EN_RD_Pos)
#define DFITMG4_DFI_TWCK_EN_RD    		DFITMG4_DFI_TWCK_EN_RD_Msk


/****************************** Bit definition for DFITMG5 register ********************************/

#define DFITMG5_DFI_TWCK_TOGGLE_POST_Pos		(0U)
#define DFITMG5_DFI_TWCK_TOGGLE_POST_Msk		(0xffUL << DFITMG5_DFI_TWCK_TOGGLE_POST_Pos)
#define DFITMG5_DFI_TWCK_TOGGLE_POST    		DFITMG5_DFI_TWCK_TOGGLE_POST_Msk


#define DFITMG5_DFI_TWCK_TOGGLE_CS_Pos		(8U)
#define DFITMG5_DFI_TWCK_TOGGLE_CS_Msk		(0xffUL << DFITMG5_DFI_TWCK_TOGGLE_CS_Pos)
#define DFITMG5_DFI_TWCK_TOGGLE_CS    		DFITMG5_DFI_TWCK_TOGGLE_CS_Msk


#define DFITMG5_DFI_TWCK_TOGGLE_Pos		(16U)
#define DFITMG5_DFI_TWCK_TOGGLE_Msk		(0xffUL << DFITMG5_DFI_TWCK_TOGGLE_Pos)
#define DFITMG5_DFI_TWCK_TOGGLE    		DFITMG5_DFI_TWCK_TOGGLE_Msk


#define DFITMG5_DFI_TWCK_FAST_TOGGLE_Pos		(24U)
#define DFITMG5_DFI_TWCK_FAST_TOGGLE_Msk		(0xffUL << DFITMG5_DFI_TWCK_FAST_TOGGLE_Pos)
#define DFITMG5_DFI_TWCK_FAST_TOGGLE    		DFITMG5_DFI_TWCK_FAST_TOGGLE_Msk


/****************************** Bit definition for DFITMG6 register ********************************/

#define DFITMG6_DFI_TWCK_TOGGLE_POST_RD_Pos		(0U)
#define DFITMG6_DFI_TWCK_TOGGLE_POST_RD_Msk		(0xffUL << DFITMG6_DFI_TWCK_TOGGLE_POST_RD_Pos)
#define DFITMG6_DFI_TWCK_TOGGLE_POST_RD    		DFITMG6_DFI_TWCK_TOGGLE_POST_RD_Msk


#define DFITMG6_DFI_TWCK_TOGGLE_POST_RD_EN_Pos		(8U)
#define DFITMG6_DFI_TWCK_TOGGLE_POST_RD_EN_Msk		(0x1UL << DFITMG6_DFI_TWCK_TOGGLE_POST_RD_EN_Pos)
#define DFITMG6_DFI_TWCK_TOGGLE_POST_RD_EN    		DFITMG6_DFI_TWCK_TOGGLE_POST_RD_EN_Msk


/****************************** Bit definition for DFILPTMG0 register ********************************/

#define DFILPTMG0_DFI_LP_WAKEUP_PD_Pos		(0U)
#define DFILPTMG0_DFI_LP_WAKEUP_PD_Msk		(0x1fUL << DFILPTMG0_DFI_LP_WAKEUP_PD_Pos)
#define DFILPTMG0_DFI_LP_WAKEUP_PD    		DFILPTMG0_DFI_LP_WAKEUP_PD_Msk


#define DFILPTMG0_DFI_LP_WAKEUP_SR_Pos		(8U)
#define DFILPTMG0_DFI_LP_WAKEUP_SR_Msk		(0x1fUL << DFILPTMG0_DFI_LP_WAKEUP_SR_Pos)
#define DFILPTMG0_DFI_LP_WAKEUP_SR    		DFILPTMG0_DFI_LP_WAKEUP_SR_Msk


#define DFILPTMG0_DFI_LP_WAKEUP_DSM_Pos		(16U)
#define DFILPTMG0_DFI_LP_WAKEUP_DSM_Msk		(0x1fUL << DFILPTMG0_DFI_LP_WAKEUP_DSM_Pos)
#define DFILPTMG0_DFI_LP_WAKEUP_DSM    		DFILPTMG0_DFI_LP_WAKEUP_DSM_Msk


/****************************** Bit definition for DFILPTMG1 register ********************************/

#define DFILPTMG1_DFI_LP_WAKEUP_DATA_Pos		(0U)
#define DFILPTMG1_DFI_LP_WAKEUP_DATA_Msk		(0x1fUL << DFILPTMG1_DFI_LP_WAKEUP_DATA_Pos)
#define DFILPTMG1_DFI_LP_WAKEUP_DATA    		DFILPTMG1_DFI_LP_WAKEUP_DATA_Msk


#define DFILPTMG1_DFI_TLP_RESP_Pos		(8U)
#define DFILPTMG1_DFI_TLP_RESP_Msk		(0x1fUL << DFILPTMG1_DFI_TLP_RESP_Pos)
#define DFILPTMG1_DFI_TLP_RESP    		DFILPTMG1_DFI_TLP_RESP_Msk


/****************************** Bit definition for DFIUPDTMG0 register ********************************/

#define DFIUPDTMG0_DFI_T_CTRLUP_MIN_Pos		(0U)
#define DFIUPDTMG0_DFI_T_CTRLUP_MIN_Msk		(0x3ffUL << DFIUPDTMG0_DFI_T_CTRLUP_MIN_Pos)
#define DFIUPDTMG0_DFI_T_CTRLUP_MIN    		DFIUPDTMG0_DFI_T_CTRLUP_MIN_Msk


#define DFIUPDTMG0_DFI_T_CTRLUP_MAX_Pos		(16U)
#define DFIUPDTMG0_DFI_T_CTRLUP_MAX_Msk		(0x3ffUL << DFIUPDTMG0_DFI_T_CTRLUP_MAX_Pos)
#define DFIUPDTMG0_DFI_T_CTRLUP_MAX    		DFIUPDTMG0_DFI_T_CTRLUP_MAX_Msk


/****************************** Bit definition for DFIUPDTMG1 register ********************************/

#define DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos		(0U)
#define DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk		(0xffUL << DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos)
#define DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024    		DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk


#define DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos		(16U)
#define DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk		(0xffUL << DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos)
#define DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024    		DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk


/****************************** Bit definition for DFIMSGTMG0 register ********************************/

#define DFIMSGTMG0_DFI_T_CTRLMSG_RESP_Pos		(0U)
#define DFIMSGTMG0_DFI_T_CTRLMSG_RESP_Msk		(0xffUL << DFIMSGTMG0_DFI_T_CTRLMSG_RESP_Pos)
#define DFIMSGTMG0_DFI_T_CTRLMSG_RESP    		DFIMSGTMG0_DFI_T_CTRLMSG_RESP_Msk


/****************************** Bit definition for DFIUPDTMG2 register ********************************/

#define DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1_Pos		(0U)
#define DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1_Msk		(0xfffUL << DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1_Pos)
#define DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1    		DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1_Msk


#define DFIUPDTMG2_PPT2_EN_Pos		(29U)
#define DFIUPDTMG2_PPT2_EN_Msk		(0x1UL << DFIUPDTMG2_PPT2_EN_Pos)
#define DFIUPDTMG2_PPT2_EN    		DFIUPDTMG2_PPT2_EN_Msk


#define DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1_UNIT_Pos		(30U)
#define DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1_UNIT_Msk		(0x3UL << DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1_UNIT_Pos)
#define DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1_UNIT    		DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1_UNIT_Msk


/****************************** Bit definition for RFSHSET1TMG0 register ********************************/

#define RFSHSET1TMG0_T_REFI_X1_X32_Pos		(0U)
#define RFSHSET1TMG0_T_REFI_X1_X32_Msk		(0x3fffUL << RFSHSET1TMG0_T_REFI_X1_X32_Pos)
#define RFSHSET1TMG0_T_REFI_X1_X32    		RFSHSET1TMG0_T_REFI_X1_X32_Msk


#define RFSHSET1TMG0_REFRESH_TO_X1_X32_Pos		(16U)
#define RFSHSET1TMG0_REFRESH_TO_X1_X32_Msk		(0x3fUL << RFSHSET1TMG0_REFRESH_TO_X1_X32_Pos)
#define RFSHSET1TMG0_REFRESH_TO_X1_X32    		RFSHSET1TMG0_REFRESH_TO_X1_X32_Msk


#define RFSHSET1TMG0_REFRESH_MARGIN_Pos		(24U)
#define RFSHSET1TMG0_REFRESH_MARGIN_Msk		(0xfUL << RFSHSET1TMG0_REFRESH_MARGIN_Pos)
#define RFSHSET1TMG0_REFRESH_MARGIN    		RFSHSET1TMG0_REFRESH_MARGIN_Msk


#define RFSHSET1TMG0_REFRESH_TO_X1_SEL_Pos		(30U)
#define RFSHSET1TMG0_REFRESH_TO_X1_SEL_Msk		(0x1UL << RFSHSET1TMG0_REFRESH_TO_X1_SEL_Pos)
#define RFSHSET1TMG0_REFRESH_TO_X1_SEL    		RFSHSET1TMG0_REFRESH_TO_X1_SEL_Msk


#define RFSHSET1TMG0_T_REFI_X1_SEL_Pos		(31U)
#define RFSHSET1TMG0_T_REFI_X1_SEL_Msk		(0x1UL << RFSHSET1TMG0_T_REFI_X1_SEL_Pos)
#define RFSHSET1TMG0_T_REFI_X1_SEL    		RFSHSET1TMG0_T_REFI_X1_SEL_Msk


/****************************** Bit definition for RFSHSET1TMG1 register ********************************/

#define RFSHSET1TMG1_T_RFC_MIN_Pos		(0U)
#define RFSHSET1TMG1_T_RFC_MIN_Msk		(0xfffUL << RFSHSET1TMG1_T_RFC_MIN_Pos)
#define RFSHSET1TMG1_T_RFC_MIN    		RFSHSET1TMG1_T_RFC_MIN_Msk


#define RFSHSET1TMG1_T_RFC_MIN_AB_Pos		(16U)
#define RFSHSET1TMG1_T_RFC_MIN_AB_Msk		(0xfffUL << RFSHSET1TMG1_T_RFC_MIN_AB_Pos)
#define RFSHSET1TMG1_T_RFC_MIN_AB    		RFSHSET1TMG1_T_RFC_MIN_AB_Msk


/****************************** Bit definition for RFSHSET1TMG2 register ********************************/

#define RFSHSET1TMG2_T_PBR2PBR_Pos		(16U)
#define RFSHSET1TMG2_T_PBR2PBR_Msk		(0xffUL << RFSHSET1TMG2_T_PBR2PBR_Pos)
#define RFSHSET1TMG2_T_PBR2PBR    		RFSHSET1TMG2_T_PBR2PBR_Msk


#define RFSHSET1TMG2_T_PBR2ACT_Pos		(24U)
#define RFSHSET1TMG2_T_PBR2ACT_Msk		(0xffUL << RFSHSET1TMG2_T_PBR2ACT_Pos)
#define RFSHSET1TMG2_T_PBR2ACT    		RFSHSET1TMG2_T_PBR2ACT_Msk


/****************************** Bit definition for RFSHSET1TMG3 register ********************************/

#define RFSHSET1TMG3_REFRESH_TO_AB_X32_Pos		(24U)
#define RFSHSET1TMG3_REFRESH_TO_AB_X32_Msk		(0x3fUL << RFSHSET1TMG3_REFRESH_TO_AB_X32_Pos)
#define RFSHSET1TMG3_REFRESH_TO_AB_X32    		RFSHSET1TMG3_REFRESH_TO_AB_X32_Msk


/****************************** Bit definition for RFSHSET1TMG4 register ********************************/

#define RFSHSET1TMG4_REFRESH_TIMER0_START_VALUE_X32_Pos		(0U)
#define RFSHSET1TMG4_REFRESH_TIMER0_START_VALUE_X32_Msk		(0xfffUL << RFSHSET1TMG4_REFRESH_TIMER0_START_VALUE_X32_Pos)
#define RFSHSET1TMG4_REFRESH_TIMER0_START_VALUE_X32    		RFSHSET1TMG4_REFRESH_TIMER0_START_VALUE_X32_Msk


#define RFSHSET1TMG4_REFRESH_TIMER1_START_VALUE_X32_Pos		(16U)
#define RFSHSET1TMG4_REFRESH_TIMER1_START_VALUE_X32_Msk		(0xfffUL << RFSHSET1TMG4_REFRESH_TIMER1_START_VALUE_X32_Pos)
#define RFSHSET1TMG4_REFRESH_TIMER1_START_VALUE_X32    		RFSHSET1TMG4_REFRESH_TIMER1_START_VALUE_X32_Msk


/****************************** Bit definition for RFMSET1TMG0 register ********************************/

#define RFMSET1TMG0_T_RFMPB_Pos		(0U)
#define RFMSET1TMG0_T_RFMPB_Msk		(0xfffUL << RFMSET1TMG0_T_RFMPB_Pos)
#define RFMSET1TMG0_T_RFMPB    		RFMSET1TMG0_T_RFMPB_Msk


/****************************** Bit definition for ZQSET1TMG0 register ********************************/

#define ZQSET1TMG0_T_ZQ_LONG_NOP_Pos		(0U)
#define ZQSET1TMG0_T_ZQ_LONG_NOP_Msk		(0x3fffUL << ZQSET1TMG0_T_ZQ_LONG_NOP_Pos)
#define ZQSET1TMG0_T_ZQ_LONG_NOP    		ZQSET1TMG0_T_ZQ_LONG_NOP_Msk


#define ZQSET1TMG0_T_ZQ_SHORT_NOP_Pos		(16U)
#define ZQSET1TMG0_T_ZQ_SHORT_NOP_Msk		(0x3ffUL << ZQSET1TMG0_T_ZQ_SHORT_NOP_Pos)
#define ZQSET1TMG0_T_ZQ_SHORT_NOP    		ZQSET1TMG0_T_ZQ_SHORT_NOP_Msk


/****************************** Bit definition for ZQSET1TMG1 register ********************************/

#define ZQSET1TMG1_T_ZQ_SHORT_INTERVAL_X1024_Pos		(0U)
#define ZQSET1TMG1_T_ZQ_SHORT_INTERVAL_X1024_Msk		(0xfffffUL << ZQSET1TMG1_T_ZQ_SHORT_INTERVAL_X1024_Pos)
#define ZQSET1TMG1_T_ZQ_SHORT_INTERVAL_X1024    		ZQSET1TMG1_T_ZQ_SHORT_INTERVAL_X1024_Msk


#define ZQSET1TMG1_T_ZQ_RESET_NOP_Pos		(20U)
#define ZQSET1TMG1_T_ZQ_RESET_NOP_Msk		(0x3ffUL << ZQSET1TMG1_T_ZQ_RESET_NOP_Pos)
#define ZQSET1TMG1_T_ZQ_RESET_NOP    		ZQSET1TMG1_T_ZQ_RESET_NOP_Msk


/****************************** Bit definition for DQSOSCCTL0 register ********************************/

#define DQSOSCCTL0_DQSOSC_ENABLE_Pos		(0U)
#define DQSOSCCTL0_DQSOSC_ENABLE_Msk		(0x1UL << DQSOSCCTL0_DQSOSC_ENABLE_Pos)
#define DQSOSCCTL0_DQSOSC_ENABLE    		DQSOSCCTL0_DQSOSC_ENABLE_Msk


#define DQSOSCCTL0_DQSOSC_INTERVAL_UNIT_Pos		(2U)
#define DQSOSCCTL0_DQSOSC_INTERVAL_UNIT_Msk		(0x1UL << DQSOSCCTL0_DQSOSC_INTERVAL_UNIT_Pos)
#define DQSOSCCTL0_DQSOSC_INTERVAL_UNIT    		DQSOSCCTL0_DQSOSC_INTERVAL_UNIT_Msk


#define DQSOSCCTL0_DQSOSC_INTERVAL_Pos		(4U)
#define DQSOSCCTL0_DQSOSC_INTERVAL_Msk		(0xfffUL << DQSOSCCTL0_DQSOSC_INTERVAL_Pos)
#define DQSOSCCTL0_DQSOSC_INTERVAL    		DQSOSCCTL0_DQSOSC_INTERVAL_Msk


/****************************** Bit definition for DERATEINT register ********************************/

#define DERATEINT_MR4_READ_INTERVAL_Pos		(0U)
#define DERATEINT_MR4_READ_INTERVAL_Msk		(0xffffffffUL << DERATEINT_MR4_READ_INTERVAL_Pos)
#define DERATEINT_MR4_READ_INTERVAL    		DERATEINT_MR4_READ_INTERVAL_Msk


/****************************** Bit definition for DERATEVAL0 register ********************************/

#define DERATEVAL0_DERATED_T_RRD_Pos		(0U)
#define DERATEVAL0_DERATED_T_RRD_Msk		(0x3fUL << DERATEVAL0_DERATED_T_RRD_Pos)
#define DERATEVAL0_DERATED_T_RRD    		DERATEVAL0_DERATED_T_RRD_Msk


#define DERATEVAL0_DERATED_T_RP_Pos		(8U)
#define DERATEVAL0_DERATED_T_RP_Msk		(0x7fUL << DERATEVAL0_DERATED_T_RP_Pos)
#define DERATEVAL0_DERATED_T_RP    		DERATEVAL0_DERATED_T_RP_Msk


#define DERATEVAL0_DERATED_T_RAS_MIN_Pos		(16U)
#define DERATEVAL0_DERATED_T_RAS_MIN_Msk		(0xffUL << DERATEVAL0_DERATED_T_RAS_MIN_Pos)
#define DERATEVAL0_DERATED_T_RAS_MIN    		DERATEVAL0_DERATED_T_RAS_MIN_Msk


#define DERATEVAL0_DERATED_T_RCD_Pos		(24U)
#define DERATEVAL0_DERATED_T_RCD_Msk		(0xffUL << DERATEVAL0_DERATED_T_RCD_Pos)
#define DERATEVAL0_DERATED_T_RCD    		DERATEVAL0_DERATED_T_RCD_Msk


/****************************** Bit definition for DERATEVAL1 register ********************************/

#define DERATEVAL1_DERATED_T_RC_Pos		(0U)
#define DERATEVAL1_DERATED_T_RC_Msk		(0xffUL << DERATEVAL1_DERATED_T_RC_Pos)
#define DERATEVAL1_DERATED_T_RC    		DERATEVAL1_DERATED_T_RC_Msk


#define DERATEVAL1_DERATED_T_RCD_WRITE_Pos		(8U)
#define DERATEVAL1_DERATED_T_RCD_WRITE_Msk		(0xffUL << DERATEVAL1_DERATED_T_RCD_WRITE_Pos)
#define DERATEVAL1_DERATED_T_RCD_WRITE    		DERATEVAL1_DERATED_T_RCD_WRITE_Msk


/****************************** Bit definition for HWLPTMG0 register ********************************/

#define HWLPTMG0_HW_LP_IDLE_X32_Pos		(16U)
#define HWLPTMG0_HW_LP_IDLE_X32_Msk		(0xfffUL << HWLPTMG0_HW_LP_IDLE_X32_Pos)
#define HWLPTMG0_HW_LP_IDLE_X32    		HWLPTMG0_HW_LP_IDLE_X32_Msk


/****************************** Bit definition for SCHEDTMG0 register ********************************/

#define SCHEDTMG0_PAGECLOSE_TIMER_Pos		(0U)
#define SCHEDTMG0_PAGECLOSE_TIMER_Msk		(0xffUL << SCHEDTMG0_PAGECLOSE_TIMER_Pos)
#define SCHEDTMG0_PAGECLOSE_TIMER    		SCHEDTMG0_PAGECLOSE_TIMER_Msk


#define SCHEDTMG0_RDWR_IDLE_GAP_Pos		(8U)
#define SCHEDTMG0_RDWR_IDLE_GAP_Msk		(0x7fUL << SCHEDTMG0_RDWR_IDLE_GAP_Pos)
#define SCHEDTMG0_RDWR_IDLE_GAP    		SCHEDTMG0_RDWR_IDLE_GAP_Msk


/****************************** Bit definition for PERFHPR1 register ********************************/

#define PERFHPR1_HPR_MAX_STARVE_Pos		(0U)
#define PERFHPR1_HPR_MAX_STARVE_Msk		(0xffffUL << PERFHPR1_HPR_MAX_STARVE_Pos)
#define PERFHPR1_HPR_MAX_STARVE    		PERFHPR1_HPR_MAX_STARVE_Msk


#define PERFHPR1_HPR_XACT_RUN_LENGTH_Pos		(24U)
#define PERFHPR1_HPR_XACT_RUN_LENGTH_Msk		(0xffUL << PERFHPR1_HPR_XACT_RUN_LENGTH_Pos)
#define PERFHPR1_HPR_XACT_RUN_LENGTH    		PERFHPR1_HPR_XACT_RUN_LENGTH_Msk


/****************************** Bit definition for PERFLPR1 register ********************************/

#define PERFLPR1_LPR_MAX_STARVE_Pos		(0U)
#define PERFLPR1_LPR_MAX_STARVE_Msk		(0xffffUL << PERFLPR1_LPR_MAX_STARVE_Pos)
#define PERFLPR1_LPR_MAX_STARVE    		PERFLPR1_LPR_MAX_STARVE_Msk


#define PERFLPR1_LPR_XACT_RUN_LENGTH_Pos		(24U)
#define PERFLPR1_LPR_XACT_RUN_LENGTH_Msk		(0xffUL << PERFLPR1_LPR_XACT_RUN_LENGTH_Pos)
#define PERFLPR1_LPR_XACT_RUN_LENGTH    		PERFLPR1_LPR_XACT_RUN_LENGTH_Msk


/****************************** Bit definition for PERFWR1 register ********************************/

#define PERFWR1_W_MAX_STARVE_Pos		(0U)
#define PERFWR1_W_MAX_STARVE_Msk		(0xffffUL << PERFWR1_W_MAX_STARVE_Pos)
#define PERFWR1_W_MAX_STARVE    		PERFWR1_W_MAX_STARVE_Msk


#define PERFWR1_W_XACT_RUN_LENGTH_Pos		(24U)
#define PERFWR1_W_XACT_RUN_LENGTH_Msk		(0xffUL << PERFWR1_W_XACT_RUN_LENGTH_Pos)
#define PERFWR1_W_XACT_RUN_LENGTH    		PERFWR1_W_XACT_RUN_LENGTH_Msk


/****************************** Bit definition for TMGCFG register ********************************/

#define TMGCFG_FREQUENCY_RATIO_Pos		(0U)
#define TMGCFG_FREQUENCY_RATIO_Msk		(0x1UL << TMGCFG_FREQUENCY_RATIO_Pos)
#define TMGCFG_FREQUENCY_RATIO    		TMGCFG_FREQUENCY_RATIO_Msk


/****************************** Bit definition for RANKTMG0 register ********************************/

#define RANKTMG0_DIFF_RANK_RD_GAP_Pos		(0U)
#define RANKTMG0_DIFF_RANK_RD_GAP_Msk		(0xffUL << RANKTMG0_DIFF_RANK_RD_GAP_Pos)
#define RANKTMG0_DIFF_RANK_RD_GAP    		RANKTMG0_DIFF_RANK_RD_GAP_Msk


#define RANKTMG0_DIFF_RANK_WR_GAP_Pos		(8U)
#define RANKTMG0_DIFF_RANK_WR_GAP_Msk		(0xffUL << RANKTMG0_DIFF_RANK_WR_GAP_Pos)
#define RANKTMG0_DIFF_RANK_WR_GAP    		RANKTMG0_DIFF_RANK_WR_GAP_Msk


/****************************** Bit definition for RANKTMG1 register ********************************/

#define RANKTMG1_WR2RD_DR_Pos		(0U)
#define RANKTMG1_WR2RD_DR_Msk		(0xffUL << RANKTMG1_WR2RD_DR_Pos)
#define RANKTMG1_WR2RD_DR    		RANKTMG1_WR2RD_DR_Msk


#define RANKTMG1_RD2WR_DR_Pos		(8U)
#define RANKTMG1_RD2WR_DR_Msk		(0xffUL << RANKTMG1_RD2WR_DR_Pos)
#define RANKTMG1_RD2WR_DR    		RANKTMG1_RD2WR_DR_Msk


/****************************** Bit definition for PWRTMG register ********************************/

#define PWRTMG_POWERDOWN_TO_X32_Pos		(0U)
#define PWRTMG_POWERDOWN_TO_X32_Msk		(0x7fUL << PWRTMG_POWERDOWN_TO_X32_Pos)
#define PWRTMG_POWERDOWN_TO_X32    		PWRTMG_POWERDOWN_TO_X32_Msk


#define PWRTMG_SELFREF_TO_X32_Pos		(16U)
#define PWRTMG_SELFREF_TO_X32_Msk		(0x3ffUL << PWRTMG_SELFREF_TO_X32_Pos)
#define PWRTMG_SELFREF_TO_X32    		PWRTMG_SELFREF_TO_X32_Msk


/****************************** Bit definition for LNKECCCTL0 register ********************************/

#define LNKECCCTL0_WR_LINK_ECC_ENABLE_Pos		(0U)
#define LNKECCCTL0_WR_LINK_ECC_ENABLE_Msk		(0x1UL << LNKECCCTL0_WR_LINK_ECC_ENABLE_Pos)
#define LNKECCCTL0_WR_LINK_ECC_ENABLE    		LNKECCCTL0_WR_LINK_ECC_ENABLE_Msk


#define LNKECCCTL0_RD_LINK_ECC_ENABLE_Pos		(1U)
#define LNKECCCTL0_RD_LINK_ECC_ENABLE_Msk		(0x1UL << LNKECCCTL0_RD_LINK_ECC_ENABLE_Pos)
#define LNKECCCTL0_RD_LINK_ECC_ENABLE    		LNKECCCTL0_RD_LINK_ECC_ENABLE_Msk


/****************************** Inline function for DRAMSET1TMG0 register ********************************/

static inline void set_dramset1tmg0_t_ras_min(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG0, DRAMSET1TMG0_T_RAS_MIN, VAL << DRAMSET1TMG0_T_RAS_MIN_Pos);
}

static inline uint32_t get_dramset1tmg0_t_ras_min(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG0, DRAMSET1TMG0_T_RAS_MIN) >> DRAMSET1TMG0_T_RAS_MIN_Pos);
}

static inline void set_dramset1tmg0_t_ras_max(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG0, DRAMSET1TMG0_T_RAS_MAX, VAL << DRAMSET1TMG0_T_RAS_MAX_Pos);
}

static inline uint32_t get_dramset1tmg0_t_ras_max(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG0, DRAMSET1TMG0_T_RAS_MAX) >> DRAMSET1TMG0_T_RAS_MAX_Pos);
}

static inline void set_dramset1tmg0_t_faw(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG0, DRAMSET1TMG0_T_FAW, VAL << DRAMSET1TMG0_T_FAW_Pos);
}

static inline uint32_t get_dramset1tmg0_t_faw(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG0, DRAMSET1TMG0_T_FAW) >> DRAMSET1TMG0_T_FAW_Pos);
}

static inline void set_dramset1tmg0_wr2pre(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG0, DRAMSET1TMG0_WR2PRE, VAL << DRAMSET1TMG0_WR2PRE_Pos);
}

static inline uint32_t get_dramset1tmg0_wr2pre(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG0, DRAMSET1TMG0_WR2PRE) >> DRAMSET1TMG0_WR2PRE_Pos);
}

/****************************** Inline function for DRAMSET1TMG1 register ********************************/

static inline void set_dramset1tmg1_t_rc(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG1, DRAMSET1TMG1_T_RC, VAL << DRAMSET1TMG1_T_RC_Pos);
}

static inline uint32_t get_dramset1tmg1_t_rc(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG1, DRAMSET1TMG1_T_RC) >> DRAMSET1TMG1_T_RC_Pos);
}

static inline void set_dramset1tmg1_rd2pre(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG1, DRAMSET1TMG1_RD2PRE, VAL << DRAMSET1TMG1_RD2PRE_Pos);
}

static inline uint32_t get_dramset1tmg1_rd2pre(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG1, DRAMSET1TMG1_RD2PRE) >> DRAMSET1TMG1_RD2PRE_Pos);
}

static inline void set_dramset1tmg1_t_xp(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG1, DRAMSET1TMG1_T_XP, VAL << DRAMSET1TMG1_T_XP_Pos);
}

static inline uint32_t get_dramset1tmg1_t_xp(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG1, DRAMSET1TMG1_T_XP) >> DRAMSET1TMG1_T_XP_Pos);
}

static inline void set_dramset1tmg1_t_rcd_write(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG1, DRAMSET1TMG1_T_RCD_WRITE, VAL << DRAMSET1TMG1_T_RCD_WRITE_Pos);
}

static inline uint32_t get_dramset1tmg1_t_rcd_write(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG1, DRAMSET1TMG1_T_RCD_WRITE) >> DRAMSET1TMG1_T_RCD_WRITE_Pos);
}

/****************************** Inline function for DRAMSET1TMG2 register ********************************/

static inline void set_dramset1tmg2_wr2rd(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG2, DRAMSET1TMG2_WR2RD, VAL << DRAMSET1TMG2_WR2RD_Pos);
}

static inline uint32_t get_dramset1tmg2_wr2rd(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG2, DRAMSET1TMG2_WR2RD) >> DRAMSET1TMG2_WR2RD_Pos);
}

static inline void set_dramset1tmg2_rd2wr(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG2, DRAMSET1TMG2_RD2WR, VAL << DRAMSET1TMG2_RD2WR_Pos);
}

static inline uint32_t get_dramset1tmg2_rd2wr(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG2, DRAMSET1TMG2_RD2WR) >> DRAMSET1TMG2_RD2WR_Pos);
}

static inline void set_dramset1tmg2_read_latency(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG2, DRAMSET1TMG2_READ_LATENCY, VAL << DRAMSET1TMG2_READ_LATENCY_Pos);
}

static inline uint32_t get_dramset1tmg2_read_latency(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG2, DRAMSET1TMG2_READ_LATENCY) >> DRAMSET1TMG2_READ_LATENCY_Pos);
}

static inline void set_dramset1tmg2_write_latency(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG2, DRAMSET1TMG2_WRITE_LATENCY, VAL << DRAMSET1TMG2_WRITE_LATENCY_Pos);
}

static inline uint32_t get_dramset1tmg2_write_latency(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG2, DRAMSET1TMG2_WRITE_LATENCY) >> DRAMSET1TMG2_WRITE_LATENCY_Pos);
}

/****************************** Inline function for DRAMSET1TMG3 register ********************************/

static inline void set_dramset1tmg3_wr2mr(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG3, DRAMSET1TMG3_WR2MR, VAL << DRAMSET1TMG3_WR2MR_Pos);
}

static inline uint32_t get_dramset1tmg3_wr2mr(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG3, DRAMSET1TMG3_WR2MR) >> DRAMSET1TMG3_WR2MR_Pos);
}

static inline void set_dramset1tmg3_rd2mr(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG3, DRAMSET1TMG3_RD2MR, VAL << DRAMSET1TMG3_RD2MR_Pos);
}

static inline uint32_t get_dramset1tmg3_rd2mr(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG3, DRAMSET1TMG3_RD2MR) >> DRAMSET1TMG3_RD2MR_Pos);
}

static inline void set_dramset1tmg3_t_mr(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG3, DRAMSET1TMG3_T_MR, VAL << DRAMSET1TMG3_T_MR_Pos);
}

static inline uint32_t get_dramset1tmg3_t_mr(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG3, DRAMSET1TMG3_T_MR) >> DRAMSET1TMG3_T_MR_Pos);
}

/****************************** Inline function for DRAMSET1TMG4 register ********************************/

static inline void set_dramset1tmg4_t_rp(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG4, DRAMSET1TMG4_T_RP, VAL << DRAMSET1TMG4_T_RP_Pos);
}

static inline uint32_t get_dramset1tmg4_t_rp(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG4, DRAMSET1TMG4_T_RP) >> DRAMSET1TMG4_T_RP_Pos);
}

static inline void set_dramset1tmg4_t_rrd(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG4, DRAMSET1TMG4_T_RRD, VAL << DRAMSET1TMG4_T_RRD_Pos);
}

static inline uint32_t get_dramset1tmg4_t_rrd(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG4, DRAMSET1TMG4_T_RRD) >> DRAMSET1TMG4_T_RRD_Pos);
}

static inline void set_dramset1tmg4_t_ccd(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG4, DRAMSET1TMG4_T_CCD, VAL << DRAMSET1TMG4_T_CCD_Pos);
}

static inline uint32_t get_dramset1tmg4_t_ccd(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG4, DRAMSET1TMG4_T_CCD) >> DRAMSET1TMG4_T_CCD_Pos);
}

static inline void set_dramset1tmg4_t_rcd(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG4, DRAMSET1TMG4_T_RCD, VAL << DRAMSET1TMG4_T_RCD_Pos);
}

static inline uint32_t get_dramset1tmg4_t_rcd(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG4, DRAMSET1TMG4_T_RCD) >> DRAMSET1TMG4_T_RCD_Pos);
}

/****************************** Inline function for DRAMSET1TMG5 register ********************************/

static inline void set_dramset1tmg5_t_cke(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG5, DRAMSET1TMG5_T_CKE, VAL << DRAMSET1TMG5_T_CKE_Pos);
}

static inline uint32_t get_dramset1tmg5_t_cke(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG5, DRAMSET1TMG5_T_CKE) >> DRAMSET1TMG5_T_CKE_Pos);
}

static inline void set_dramset1tmg5_t_ckesr(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG5, DRAMSET1TMG5_T_CKESR, VAL << DRAMSET1TMG5_T_CKESR_Pos);
}

static inline uint32_t get_dramset1tmg5_t_ckesr(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG5, DRAMSET1TMG5_T_CKESR) >> DRAMSET1TMG5_T_CKESR_Pos);
}

static inline void set_dramset1tmg5_t_cksre(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG5, DRAMSET1TMG5_T_CKSRE, VAL << DRAMSET1TMG5_T_CKSRE_Pos);
}

static inline uint32_t get_dramset1tmg5_t_cksre(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG5, DRAMSET1TMG5_T_CKSRE) >> DRAMSET1TMG5_T_CKSRE_Pos);
}

static inline void set_dramset1tmg5_t_cksrx(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG5, DRAMSET1TMG5_T_CKSRX, VAL << DRAMSET1TMG5_T_CKSRX_Pos);
}

static inline uint32_t get_dramset1tmg5_t_cksrx(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG5, DRAMSET1TMG5_T_CKSRX) >> DRAMSET1TMG5_T_CKSRX_Pos);
}

/****************************** Inline function for DRAMSET1TMG6 register ********************************/

static inline void set_dramset1tmg6_t_ckcsx(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG6, DRAMSET1TMG6_T_CKCSX, VAL << DRAMSET1TMG6_T_CKCSX_Pos);
}

static inline uint32_t get_dramset1tmg6_t_ckcsx(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG6, DRAMSET1TMG6_T_CKCSX) >> DRAMSET1TMG6_T_CKCSX_Pos);
}

/****************************** Inline function for DRAMSET1TMG7 register ********************************/

static inline void set_dramset1tmg7_t_csh(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG7, DRAMSET1TMG7_T_CSH, VAL << DRAMSET1TMG7_T_CSH_Pos);
}

static inline uint32_t get_dramset1tmg7_t_csh(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG7, DRAMSET1TMG7_T_CSH) >> DRAMSET1TMG7_T_CSH_Pos);
}

/****************************** Inline function for DRAMSET1TMG9 register ********************************/

static inline void set_dramset1tmg9_wr2rd_s(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG9, DRAMSET1TMG9_WR2RD_S, VAL << DRAMSET1TMG9_WR2RD_S_Pos);
}

static inline uint32_t get_dramset1tmg9_wr2rd_s(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG9, DRAMSET1TMG9_WR2RD_S) >> DRAMSET1TMG9_WR2RD_S_Pos);
}

static inline void set_dramset1tmg9_t_rrd_s(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG9, DRAMSET1TMG9_T_RRD_S, VAL << DRAMSET1TMG9_T_RRD_S_Pos);
}

static inline uint32_t get_dramset1tmg9_t_rrd_s(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG9, DRAMSET1TMG9_T_RRD_S) >> DRAMSET1TMG9_T_RRD_S_Pos);
}

static inline void set_dramset1tmg9_t_ccd_s(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG9, DRAMSET1TMG9_T_CCD_S, VAL << DRAMSET1TMG9_T_CCD_S_Pos);
}

static inline uint32_t get_dramset1tmg9_t_ccd_s(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG9, DRAMSET1TMG9_T_CCD_S) >> DRAMSET1TMG9_T_CCD_S_Pos);
}

/****************************** Inline function for DRAMSET1TMG12 register ********************************/

static inline void set_dramset1tmg12_t_cmdcke(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG12, DRAMSET1TMG12_T_CMDCKE, VAL << DRAMSET1TMG12_T_CMDCKE_Pos);
}

static inline uint32_t get_dramset1tmg12_t_cmdcke(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG12, DRAMSET1TMG12_T_CMDCKE) >> DRAMSET1TMG12_T_CMDCKE_Pos);
}

/****************************** Inline function for DRAMSET1TMG13 register ********************************/

static inline void set_dramset1tmg13_t_ppd(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG13, DRAMSET1TMG13_T_PPD, VAL << DRAMSET1TMG13_T_PPD_Pos);
}

static inline uint32_t get_dramset1tmg13_t_ppd(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG13, DRAMSET1TMG13_T_PPD) >> DRAMSET1TMG13_T_PPD_Pos);
}

static inline void set_dramset1tmg13_t_ccd_mw(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG13, DRAMSET1TMG13_T_CCD_MW, VAL << DRAMSET1TMG13_T_CCD_MW_Pos);
}

static inline uint32_t get_dramset1tmg13_t_ccd_mw(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG13, DRAMSET1TMG13_T_CCD_MW) >> DRAMSET1TMG13_T_CCD_MW_Pos);
}

static inline void set_dramset1tmg13_odtloff(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG13, DRAMSET1TMG13_ODTLOFF, VAL << DRAMSET1TMG13_ODTLOFF_Pos);
}

static inline uint32_t get_dramset1tmg13_odtloff(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG13, DRAMSET1TMG13_ODTLOFF) >> DRAMSET1TMG13_ODTLOFF_Pos);
}

/****************************** Inline function for DRAMSET1TMG14 register ********************************/

static inline void set_dramset1tmg14_t_xsr(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG14, DRAMSET1TMG14_T_XSR, VAL << DRAMSET1TMG14_T_XSR_Pos);
}

static inline uint32_t get_dramset1tmg14_t_xsr(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG14, DRAMSET1TMG14_T_XSR) >> DRAMSET1TMG14_T_XSR_Pos);
}

static inline void set_dramset1tmg14_t_osco(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG14, DRAMSET1TMG14_T_OSCO, VAL << DRAMSET1TMG14_T_OSCO_Pos);
}

static inline uint32_t get_dramset1tmg14_t_osco(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG14, DRAMSET1TMG14_T_OSCO) >> DRAMSET1TMG14_T_OSCO_Pos);
}

/****************************** Inline function for DRAMSET1TMG23 register ********************************/

static inline void set_dramset1tmg23_t_pdn(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG23, DRAMSET1TMG23_T_PDN, VAL << DRAMSET1TMG23_T_PDN_Pos);
}

static inline uint32_t get_dramset1tmg23_t_pdn(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG23, DRAMSET1TMG23_T_PDN) >> DRAMSET1TMG23_T_PDN_Pos);
}

static inline void set_dramset1tmg23_t_xsr_dsm_x1024(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG23, DRAMSET1TMG23_T_XSR_DSM_X1024, VAL << DRAMSET1TMG23_T_XSR_DSM_X1024_Pos);
}

static inline uint32_t get_dramset1tmg23_t_xsr_dsm_x1024(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG23, DRAMSET1TMG23_T_XSR_DSM_X1024) >> DRAMSET1TMG23_T_XSR_DSM_X1024_Pos);
}

/****************************** Inline function for DRAMSET1TMG24 register ********************************/

static inline void set_dramset1tmg24_max_wr_sync(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG24, DRAMSET1TMG24_MAX_WR_SYNC, VAL << DRAMSET1TMG24_MAX_WR_SYNC_Pos);
}

static inline uint32_t get_dramset1tmg24_max_wr_sync(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG24, DRAMSET1TMG24_MAX_WR_SYNC) >> DRAMSET1TMG24_MAX_WR_SYNC_Pos);
}

static inline void set_dramset1tmg24_max_rd_sync(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG24, DRAMSET1TMG24_MAX_RD_SYNC, VAL << DRAMSET1TMG24_MAX_RD_SYNC_Pos);
}

static inline uint32_t get_dramset1tmg24_max_rd_sync(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG24, DRAMSET1TMG24_MAX_RD_SYNC) >> DRAMSET1TMG24_MAX_RD_SYNC_Pos);
}

static inline void set_dramset1tmg24_rd2wr_s(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG24, DRAMSET1TMG24_RD2WR_S, VAL << DRAMSET1TMG24_RD2WR_S_Pos);
}

static inline uint32_t get_dramset1tmg24_rd2wr_s(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG24, DRAMSET1TMG24_RD2WR_S) >> DRAMSET1TMG24_RD2WR_S_Pos);
}

static inline void set_dramset1tmg24_bank_org(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG24, DRAMSET1TMG24_BANK_ORG, VAL << DRAMSET1TMG24_BANK_ORG_Pos);
}

static inline uint32_t get_dramset1tmg24_bank_org(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG24, DRAMSET1TMG24_BANK_ORG) >> DRAMSET1TMG24_BANK_ORG_Pos);
}

/****************************** Inline function for DRAMSET1TMG25 register ********************************/

static inline void set_dramset1tmg25_rda2pre(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG25, DRAMSET1TMG25_RDA2PRE, VAL << DRAMSET1TMG25_RDA2PRE_Pos);
}

static inline uint32_t get_dramset1tmg25_rda2pre(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG25, DRAMSET1TMG25_RDA2PRE) >> DRAMSET1TMG25_RDA2PRE_Pos);
}

static inline void set_dramset1tmg25_wra2pre(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG25, DRAMSET1TMG25_WRA2PRE, VAL << DRAMSET1TMG25_WRA2PRE_Pos);
}

static inline uint32_t get_dramset1tmg25_wra2pre(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG25, DRAMSET1TMG25_WRA2PRE) >> DRAMSET1TMG25_WRA2PRE_Pos);
}

static inline void set_dramset1tmg25_lpddr4_diff_bank_rwa2pre(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG25, DRAMSET1TMG25_LPDDR4_DIFF_BANK_RWA2PRE, VAL << DRAMSET1TMG25_LPDDR4_DIFF_BANK_RWA2PRE_Pos);
}

static inline uint32_t get_dramset1tmg25_lpddr4_diff_bank_rwa2pre(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG25, DRAMSET1TMG25_LPDDR4_DIFF_BANK_RWA2PRE) >> DRAMSET1TMG25_LPDDR4_DIFF_BANK_RWA2PRE_Pos);
}

/****************************** Inline function for DRAMSET1TMG30 register ********************************/

static inline void set_dramset1tmg30_mrr2rd(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG30, DRAMSET1TMG30_MRR2RD, VAL << DRAMSET1TMG30_MRR2RD_Pos);
}

static inline uint32_t get_dramset1tmg30_mrr2rd(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG30, DRAMSET1TMG30_MRR2RD) >> DRAMSET1TMG30_MRR2RD_Pos);
}

static inline void set_dramset1tmg30_mrr2wr(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG30, DRAMSET1TMG30_MRR2WR, VAL << DRAMSET1TMG30_MRR2WR_Pos);
}

static inline uint32_t get_dramset1tmg30_mrr2wr(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG30, DRAMSET1TMG30_MRR2WR) >> DRAMSET1TMG30_MRR2WR_Pos);
}

static inline void set_dramset1tmg30_mrr2mrw(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG30, DRAMSET1TMG30_MRR2MRW, VAL << DRAMSET1TMG30_MRR2MRW_Pos);
}

static inline uint32_t get_dramset1tmg30_mrr2mrw(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG30, DRAMSET1TMG30_MRR2MRW) >> DRAMSET1TMG30_MRR2MRW_Pos);
}

/****************************** Inline function for DRAMSET1TMG32 register ********************************/

static inline void set_dramset1tmg32_ws_fs2wck_sus(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG32, DRAMSET1TMG32_WS_FS2WCK_SUS, VAL << DRAMSET1TMG32_WS_FS2WCK_SUS_Pos);
}

static inline uint32_t get_dramset1tmg32_ws_fs2wck_sus(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG32, DRAMSET1TMG32_WS_FS2WCK_SUS) >> DRAMSET1TMG32_WS_FS2WCK_SUS_Pos);
}

static inline void set_dramset1tmg32_t_wcksus(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG32, DRAMSET1TMG32_T_WCKSUS, VAL << DRAMSET1TMG32_T_WCKSUS_Pos);
}

static inline uint32_t get_dramset1tmg32_t_wcksus(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG32, DRAMSET1TMG32_T_WCKSUS) >> DRAMSET1TMG32_T_WCKSUS_Pos);
}

static inline void set_dramset1tmg32_ws_off2ws_fs(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DRAMSET1TMG32, DRAMSET1TMG32_WS_OFF2WS_FS, VAL << DRAMSET1TMG32_WS_OFF2WS_FS_Pos);
}

static inline uint32_t get_dramset1tmg32_ws_off2ws_fs(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DRAMSET1TMG32, DRAMSET1TMG32_WS_OFF2WS_FS) >> DRAMSET1TMG32_WS_OFF2WS_FS_Pos);
}

/****************************** Inline function for INITMR0 register ********************************/

static inline void set_initmr0_emr(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->INITMR0, INITMR0_EMR, VAL << INITMR0_EMR_Pos);
}

static inline uint32_t get_initmr0_emr(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->INITMR0, INITMR0_EMR) >> INITMR0_EMR_Pos);
}

static inline void set_initmr0_mr(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->INITMR0, INITMR0_MR, VAL << INITMR0_MR_Pos);
}

static inline uint32_t get_initmr0_mr(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->INITMR0, INITMR0_MR) >> INITMR0_MR_Pos);
}

/****************************** Inline function for INITMR1 register ********************************/

static inline void set_initmr1_emr3(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->INITMR1, INITMR1_EMR3, VAL << INITMR1_EMR3_Pos);
}

static inline uint32_t get_initmr1_emr3(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->INITMR1, INITMR1_EMR3) >> INITMR1_EMR3_Pos);
}

static inline void set_initmr1_emr2(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->INITMR1, INITMR1_EMR2, VAL << INITMR1_EMR2_Pos);
}

static inline uint32_t get_initmr1_emr2(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->INITMR1, INITMR1_EMR2) >> INITMR1_EMR2_Pos);
}

/****************************** Inline function for INITMR2 register ********************************/

static inline void set_initmr2_mr5(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->INITMR2, INITMR2_MR5, VAL << INITMR2_MR5_Pos);
}

static inline uint32_t get_initmr2_mr5(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->INITMR2, INITMR2_MR5) >> INITMR2_MR5_Pos);
}

static inline void set_initmr2_mr4(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->INITMR2, INITMR2_MR4, VAL << INITMR2_MR4_Pos);
}

static inline uint32_t get_initmr2_mr4(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->INITMR2, INITMR2_MR4) >> INITMR2_MR4_Pos);
}

/****************************** Inline function for INITMR3 register ********************************/

static inline void set_initmr3_mr6(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->INITMR3, INITMR3_MR6, VAL << INITMR3_MR6_Pos);
}

static inline uint32_t get_initmr3_mr6(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->INITMR3, INITMR3_MR6) >> INITMR3_MR6_Pos);
}

static inline void set_initmr3_mr22(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->INITMR3, INITMR3_MR22, VAL << INITMR3_MR22_Pos);
}

static inline uint32_t get_initmr3_mr22(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->INITMR3, INITMR3_MR22) >> INITMR3_MR22_Pos);
}

/****************************** Inline function for DFITMG0 register ********************************/

static inline void set_dfitmg0_dfi_tphy_wrlat(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG0, DFITMG0_DFI_TPHY_WRLAT, VAL << DFITMG0_DFI_TPHY_WRLAT_Pos);
}

static inline uint32_t get_dfitmg0_dfi_tphy_wrlat(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG0, DFITMG0_DFI_TPHY_WRLAT) >> DFITMG0_DFI_TPHY_WRLAT_Pos);
}

static inline void set_dfitmg0_dfi_tphy_wrdata(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG0, DFITMG0_DFI_TPHY_WRDATA, VAL << DFITMG0_DFI_TPHY_WRDATA_Pos);
}

static inline uint32_t get_dfitmg0_dfi_tphy_wrdata(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG0, DFITMG0_DFI_TPHY_WRDATA) >> DFITMG0_DFI_TPHY_WRDATA_Pos);
}

static inline void set_dfitmg0_dfi_t_rddata_en(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG0, DFITMG0_DFI_T_RDDATA_EN, VAL << DFITMG0_DFI_T_RDDATA_EN_Pos);
}

static inline uint32_t get_dfitmg0_dfi_t_rddata_en(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG0, DFITMG0_DFI_T_RDDATA_EN) >> DFITMG0_DFI_T_RDDATA_EN_Pos);
}

static inline void set_dfitmg0_dfi_t_ctrl_delay(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG0, DFITMG0_DFI_T_CTRL_DELAY, VAL << DFITMG0_DFI_T_CTRL_DELAY_Pos);
}

static inline uint32_t get_dfitmg0_dfi_t_ctrl_delay(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG0, DFITMG0_DFI_T_CTRL_DELAY) >> DFITMG0_DFI_T_CTRL_DELAY_Pos);
}

/****************************** Inline function for DFITMG1 register ********************************/

static inline void set_dfitmg1_dfi_t_dram_clk_enable(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG1, DFITMG1_DFI_T_DRAM_CLK_ENABLE, VAL << DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos);
}

static inline uint32_t get_dfitmg1_dfi_t_dram_clk_enable(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG1, DFITMG1_DFI_T_DRAM_CLK_ENABLE) >> DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos);
}

static inline void set_dfitmg1_dfi_t_dram_clk_disable(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG1, DFITMG1_DFI_T_DRAM_CLK_DISABLE, VAL << DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos);
}

static inline uint32_t get_dfitmg1_dfi_t_dram_clk_disable(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG1, DFITMG1_DFI_T_DRAM_CLK_DISABLE) >> DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos);
}

static inline void set_dfitmg1_dfi_t_wrdata_delay(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG1, DFITMG1_DFI_T_WRDATA_DELAY, VAL << DFITMG1_DFI_T_WRDATA_DELAY_Pos);
}

static inline uint32_t get_dfitmg1_dfi_t_wrdata_delay(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG1, DFITMG1_DFI_T_WRDATA_DELAY) >> DFITMG1_DFI_T_WRDATA_DELAY_Pos);
}

/****************************** Inline function for DFITMG2 register ********************************/

static inline void set_dfitmg2_dfi_tphy_wrcslat(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG2, DFITMG2_DFI_TPHY_WRCSLAT, VAL << DFITMG2_DFI_TPHY_WRCSLAT_Pos);
}

static inline uint32_t get_dfitmg2_dfi_tphy_wrcslat(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG2, DFITMG2_DFI_TPHY_WRCSLAT) >> DFITMG2_DFI_TPHY_WRCSLAT_Pos);
}

static inline void set_dfitmg2_dfi_tphy_rdcslat(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG2, DFITMG2_DFI_TPHY_RDCSLAT, VAL << DFITMG2_DFI_TPHY_RDCSLAT_Pos);
}

static inline uint32_t get_dfitmg2_dfi_tphy_rdcslat(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG2, DFITMG2_DFI_TPHY_RDCSLAT) >> DFITMG2_DFI_TPHY_RDCSLAT_Pos);
}

static inline void set_dfitmg2_dfi_twck_delay(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG2, DFITMG2_DFI_TWCK_DELAY, VAL << DFITMG2_DFI_TWCK_DELAY_Pos);
}

static inline uint32_t get_dfitmg2_dfi_twck_delay(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG2, DFITMG2_DFI_TWCK_DELAY) >> DFITMG2_DFI_TWCK_DELAY_Pos);
}

/****************************** Inline function for DFITMG4 register ********************************/

static inline void set_dfitmg4_dfi_twck_dis(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG4, DFITMG4_DFI_TWCK_DIS, VAL << DFITMG4_DFI_TWCK_DIS_Pos);
}

static inline uint32_t get_dfitmg4_dfi_twck_dis(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG4, DFITMG4_DFI_TWCK_DIS) >> DFITMG4_DFI_TWCK_DIS_Pos);
}

static inline void set_dfitmg4_dfi_twck_en_fs(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG4, DFITMG4_DFI_TWCK_EN_FS, VAL << DFITMG4_DFI_TWCK_EN_FS_Pos);
}

static inline uint32_t get_dfitmg4_dfi_twck_en_fs(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG4, DFITMG4_DFI_TWCK_EN_FS) >> DFITMG4_DFI_TWCK_EN_FS_Pos);
}

static inline void set_dfitmg4_dfi_twck_en_wr(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG4, DFITMG4_DFI_TWCK_EN_WR, VAL << DFITMG4_DFI_TWCK_EN_WR_Pos);
}

static inline uint32_t get_dfitmg4_dfi_twck_en_wr(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG4, DFITMG4_DFI_TWCK_EN_WR) >> DFITMG4_DFI_TWCK_EN_WR_Pos);
}

static inline void set_dfitmg4_dfi_twck_en_rd(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG4, DFITMG4_DFI_TWCK_EN_RD, VAL << DFITMG4_DFI_TWCK_EN_RD_Pos);
}

static inline uint32_t get_dfitmg4_dfi_twck_en_rd(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG4, DFITMG4_DFI_TWCK_EN_RD) >> DFITMG4_DFI_TWCK_EN_RD_Pos);
}

/****************************** Inline function for DFITMG5 register ********************************/

static inline void set_dfitmg5_dfi_twck_toggle_post(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG5, DFITMG5_DFI_TWCK_TOGGLE_POST, VAL << DFITMG5_DFI_TWCK_TOGGLE_POST_Pos);
}

static inline uint32_t get_dfitmg5_dfi_twck_toggle_post(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG5, DFITMG5_DFI_TWCK_TOGGLE_POST) >> DFITMG5_DFI_TWCK_TOGGLE_POST_Pos);
}

static inline void set_dfitmg5_dfi_twck_toggle_cs(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG5, DFITMG5_DFI_TWCK_TOGGLE_CS, VAL << DFITMG5_DFI_TWCK_TOGGLE_CS_Pos);
}

static inline uint32_t get_dfitmg5_dfi_twck_toggle_cs(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG5, DFITMG5_DFI_TWCK_TOGGLE_CS) >> DFITMG5_DFI_TWCK_TOGGLE_CS_Pos);
}

static inline void set_dfitmg5_dfi_twck_toggle(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG5, DFITMG5_DFI_TWCK_TOGGLE, VAL << DFITMG5_DFI_TWCK_TOGGLE_Pos);
}

static inline uint32_t get_dfitmg5_dfi_twck_toggle(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG5, DFITMG5_DFI_TWCK_TOGGLE) >> DFITMG5_DFI_TWCK_TOGGLE_Pos);
}

static inline void set_dfitmg5_dfi_twck_fast_toggle(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG5, DFITMG5_DFI_TWCK_FAST_TOGGLE, VAL << DFITMG5_DFI_TWCK_FAST_TOGGLE_Pos);
}

static inline uint32_t get_dfitmg5_dfi_twck_fast_toggle(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG5, DFITMG5_DFI_TWCK_FAST_TOGGLE) >> DFITMG5_DFI_TWCK_FAST_TOGGLE_Pos);
}

/****************************** Inline function for DFITMG6 register ********************************/

static inline void set_dfitmg6_dfi_twck_toggle_post_rd(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG6, DFITMG6_DFI_TWCK_TOGGLE_POST_RD, VAL << DFITMG6_DFI_TWCK_TOGGLE_POST_RD_Pos);
}

static inline uint32_t get_dfitmg6_dfi_twck_toggle_post_rd(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG6, DFITMG6_DFI_TWCK_TOGGLE_POST_RD) >> DFITMG6_DFI_TWCK_TOGGLE_POST_RD_Pos);
}

static inline void set_dfitmg6_dfi_twck_toggle_post_rd_en(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFITMG6, DFITMG6_DFI_TWCK_TOGGLE_POST_RD_EN, VAL << DFITMG6_DFI_TWCK_TOGGLE_POST_RD_EN_Pos);
}

static inline uint32_t get_dfitmg6_dfi_twck_toggle_post_rd_en(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFITMG6, DFITMG6_DFI_TWCK_TOGGLE_POST_RD_EN) >> DFITMG6_DFI_TWCK_TOGGLE_POST_RD_EN_Pos);
}

/****************************** Inline function for DFILPTMG0 register ********************************/

static inline void set_dfilptmg0_dfi_lp_wakeup_pd(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFILPTMG0, DFILPTMG0_DFI_LP_WAKEUP_PD, VAL << DFILPTMG0_DFI_LP_WAKEUP_PD_Pos);
}

static inline uint32_t get_dfilptmg0_dfi_lp_wakeup_pd(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFILPTMG0, DFILPTMG0_DFI_LP_WAKEUP_PD) >> DFILPTMG0_DFI_LP_WAKEUP_PD_Pos);
}

static inline void set_dfilptmg0_dfi_lp_wakeup_sr(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFILPTMG0, DFILPTMG0_DFI_LP_WAKEUP_SR, VAL << DFILPTMG0_DFI_LP_WAKEUP_SR_Pos);
}

static inline uint32_t get_dfilptmg0_dfi_lp_wakeup_sr(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFILPTMG0, DFILPTMG0_DFI_LP_WAKEUP_SR) >> DFILPTMG0_DFI_LP_WAKEUP_SR_Pos);
}

static inline void set_dfilptmg0_dfi_lp_wakeup_dsm(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFILPTMG0, DFILPTMG0_DFI_LP_WAKEUP_DSM, VAL << DFILPTMG0_DFI_LP_WAKEUP_DSM_Pos);
}

static inline uint32_t get_dfilptmg0_dfi_lp_wakeup_dsm(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFILPTMG0, DFILPTMG0_DFI_LP_WAKEUP_DSM) >> DFILPTMG0_DFI_LP_WAKEUP_DSM_Pos);
}

/****************************** Inline function for DFILPTMG1 register ********************************/

static inline void set_dfilptmg1_dfi_lp_wakeup_data(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFILPTMG1, DFILPTMG1_DFI_LP_WAKEUP_DATA, VAL << DFILPTMG1_DFI_LP_WAKEUP_DATA_Pos);
}

static inline uint32_t get_dfilptmg1_dfi_lp_wakeup_data(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFILPTMG1, DFILPTMG1_DFI_LP_WAKEUP_DATA) >> DFILPTMG1_DFI_LP_WAKEUP_DATA_Pos);
}

static inline void set_dfilptmg1_dfi_tlp_resp(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFILPTMG1, DFILPTMG1_DFI_TLP_RESP, VAL << DFILPTMG1_DFI_TLP_RESP_Pos);
}

static inline uint32_t get_dfilptmg1_dfi_tlp_resp(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFILPTMG1, DFILPTMG1_DFI_TLP_RESP) >> DFILPTMG1_DFI_TLP_RESP_Pos);
}

/****************************** Inline function for DFIUPDTMG0 register ********************************/

static inline void set_dfiupdtmg0_dfi_t_ctrlup_min(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIUPDTMG0, DFIUPDTMG0_DFI_T_CTRLUP_MIN, VAL << DFIUPDTMG0_DFI_T_CTRLUP_MIN_Pos);
}

static inline uint32_t get_dfiupdtmg0_dfi_t_ctrlup_min(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIUPDTMG0, DFIUPDTMG0_DFI_T_CTRLUP_MIN) >> DFIUPDTMG0_DFI_T_CTRLUP_MIN_Pos);
}

static inline void set_dfiupdtmg0_dfi_t_ctrlup_max(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIUPDTMG0, DFIUPDTMG0_DFI_T_CTRLUP_MAX, VAL << DFIUPDTMG0_DFI_T_CTRLUP_MAX_Pos);
}

static inline uint32_t get_dfiupdtmg0_dfi_t_ctrlup_max(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIUPDTMG0, DFIUPDTMG0_DFI_T_CTRLUP_MAX) >> DFIUPDTMG0_DFI_T_CTRLUP_MAX_Pos);
}

/****************************** Inline function for DFIUPDTMG1 register ********************************/

static inline void set_dfiupdtmg1_dfi_t_ctrlupd_interval_max_x1024(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIUPDTMG1, DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024, VAL << DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos);
}

static inline uint32_t get_dfiupdtmg1_dfi_t_ctrlupd_interval_max_x1024(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIUPDTMG1, DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024) >> DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos);
}

static inline void set_dfiupdtmg1_dfi_t_ctrlupd_interval_min_x1024(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIUPDTMG1, DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024, VAL << DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos);
}

static inline uint32_t get_dfiupdtmg1_dfi_t_ctrlupd_interval_min_x1024(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIUPDTMG1, DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024) >> DFIUPDTMG1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos);
}

/****************************** Inline function for DFIMSGTMG0 register ********************************/

static inline void set_dfimsgtmg0_dfi_t_ctrlmsg_resp(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIMSGTMG0, DFIMSGTMG0_DFI_T_CTRLMSG_RESP, VAL << DFIMSGTMG0_DFI_T_CTRLMSG_RESP_Pos);
}

static inline uint32_t get_dfimsgtmg0_dfi_t_ctrlmsg_resp(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIMSGTMG0, DFIMSGTMG0_DFI_T_CTRLMSG_RESP) >> DFIMSGTMG0_DFI_T_CTRLMSG_RESP_Pos);
}

/****************************** Inline function for DFIUPDTMG2 register ********************************/

static inline void set_dfiupdtmg2_dfi_t_ctrlupd_interval_type1(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIUPDTMG2, DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1, VAL << DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1_Pos);
}

static inline uint32_t get_dfiupdtmg2_dfi_t_ctrlupd_interval_type1(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIUPDTMG2, DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1) >> DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1_Pos);
}

static inline void set_dfiupdtmg2_ppt2_en(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIUPDTMG2, DFIUPDTMG2_PPT2_EN, VAL << DFIUPDTMG2_PPT2_EN_Pos);
}

static inline uint32_t get_dfiupdtmg2_ppt2_en(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIUPDTMG2, DFIUPDTMG2_PPT2_EN) >> DFIUPDTMG2_PPT2_EN_Pos);
}

static inline void set_dfiupdtmg2_dfi_t_ctrlupd_interval_type1_unit(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIUPDTMG2, DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1_UNIT, VAL << DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1_UNIT_Pos);
}

static inline uint32_t get_dfiupdtmg2_dfi_t_ctrlupd_interval_type1_unit(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIUPDTMG2, DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1_UNIT) >> DFIUPDTMG2_DFI_T_CTRLUPD_INTERVAL_TYPE1_UNIT_Pos);
}

/****************************** Inline function for RFSHSET1TMG0 register ********************************/

static inline void set_rfshset1tmg0_t_refi_x1_x32(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHSET1TMG0, RFSHSET1TMG0_T_REFI_X1_X32, VAL << RFSHSET1TMG0_T_REFI_X1_X32_Pos);
}

static inline uint32_t get_rfshset1tmg0_t_refi_x1_x32(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHSET1TMG0, RFSHSET1TMG0_T_REFI_X1_X32) >> RFSHSET1TMG0_T_REFI_X1_X32_Pos);
}

static inline void set_rfshset1tmg0_refresh_to_x1_x32(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHSET1TMG0, RFSHSET1TMG0_REFRESH_TO_X1_X32, VAL << RFSHSET1TMG0_REFRESH_TO_X1_X32_Pos);
}

static inline uint32_t get_rfshset1tmg0_refresh_to_x1_x32(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHSET1TMG0, RFSHSET1TMG0_REFRESH_TO_X1_X32) >> RFSHSET1TMG0_REFRESH_TO_X1_X32_Pos);
}

static inline void set_rfshset1tmg0_refresh_margin(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHSET1TMG0, RFSHSET1TMG0_REFRESH_MARGIN, VAL << RFSHSET1TMG0_REFRESH_MARGIN_Pos);
}

static inline uint32_t get_rfshset1tmg0_refresh_margin(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHSET1TMG0, RFSHSET1TMG0_REFRESH_MARGIN) >> RFSHSET1TMG0_REFRESH_MARGIN_Pos);
}

static inline void set_rfshset1tmg0_refresh_to_x1_sel(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHSET1TMG0, RFSHSET1TMG0_REFRESH_TO_X1_SEL, VAL << RFSHSET1TMG0_REFRESH_TO_X1_SEL_Pos);
}

static inline uint32_t get_rfshset1tmg0_refresh_to_x1_sel(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHSET1TMG0, RFSHSET1TMG0_REFRESH_TO_X1_SEL) >> RFSHSET1TMG0_REFRESH_TO_X1_SEL_Pos);
}

static inline void set_rfshset1tmg0_t_refi_x1_sel(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHSET1TMG0, RFSHSET1TMG0_T_REFI_X1_SEL, VAL << RFSHSET1TMG0_T_REFI_X1_SEL_Pos);
}

static inline uint32_t get_rfshset1tmg0_t_refi_x1_sel(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHSET1TMG0, RFSHSET1TMG0_T_REFI_X1_SEL) >> RFSHSET1TMG0_T_REFI_X1_SEL_Pos);
}

/****************************** Inline function for RFSHSET1TMG1 register ********************************/

static inline void set_rfshset1tmg1_t_rfc_min(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHSET1TMG1, RFSHSET1TMG1_T_RFC_MIN, VAL << RFSHSET1TMG1_T_RFC_MIN_Pos);
}

static inline uint32_t get_rfshset1tmg1_t_rfc_min(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHSET1TMG1, RFSHSET1TMG1_T_RFC_MIN) >> RFSHSET1TMG1_T_RFC_MIN_Pos);
}

static inline void set_rfshset1tmg1_t_rfc_min_ab(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHSET1TMG1, RFSHSET1TMG1_T_RFC_MIN_AB, VAL << RFSHSET1TMG1_T_RFC_MIN_AB_Pos);
}

static inline uint32_t get_rfshset1tmg1_t_rfc_min_ab(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHSET1TMG1, RFSHSET1TMG1_T_RFC_MIN_AB) >> RFSHSET1TMG1_T_RFC_MIN_AB_Pos);
}

/****************************** Inline function for RFSHSET1TMG2 register ********************************/

static inline void set_rfshset1tmg2_t_pbr2pbr(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHSET1TMG2, RFSHSET1TMG2_T_PBR2PBR, VAL << RFSHSET1TMG2_T_PBR2PBR_Pos);
}

static inline uint32_t get_rfshset1tmg2_t_pbr2pbr(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHSET1TMG2, RFSHSET1TMG2_T_PBR2PBR) >> RFSHSET1TMG2_T_PBR2PBR_Pos);
}

static inline void set_rfshset1tmg2_t_pbr2act(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHSET1TMG2, RFSHSET1TMG2_T_PBR2ACT, VAL << RFSHSET1TMG2_T_PBR2ACT_Pos);
}

static inline uint32_t get_rfshset1tmg2_t_pbr2act(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHSET1TMG2, RFSHSET1TMG2_T_PBR2ACT) >> RFSHSET1TMG2_T_PBR2ACT_Pos);
}

/****************************** Inline function for RFSHSET1TMG3 register ********************************/

static inline void set_rfshset1tmg3_refresh_to_ab_x32(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHSET1TMG3, RFSHSET1TMG3_REFRESH_TO_AB_X32, VAL << RFSHSET1TMG3_REFRESH_TO_AB_X32_Pos);
}

static inline uint32_t get_rfshset1tmg3_refresh_to_ab_x32(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHSET1TMG3, RFSHSET1TMG3_REFRESH_TO_AB_X32) >> RFSHSET1TMG3_REFRESH_TO_AB_X32_Pos);
}

/****************************** Inline function for RFSHSET1TMG4 register ********************************/

static inline void set_rfshset1tmg4_refresh_timer0_start_value_x32(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHSET1TMG4, RFSHSET1TMG4_REFRESH_TIMER0_START_VALUE_X32, VAL << RFSHSET1TMG4_REFRESH_TIMER0_START_VALUE_X32_Pos);
}

static inline uint32_t get_rfshset1tmg4_refresh_timer0_start_value_x32(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHSET1TMG4, RFSHSET1TMG4_REFRESH_TIMER0_START_VALUE_X32) >> RFSHSET1TMG4_REFRESH_TIMER0_START_VALUE_X32_Pos);
}

static inline void set_rfshset1tmg4_refresh_timer1_start_value_x32(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHSET1TMG4, RFSHSET1TMG4_REFRESH_TIMER1_START_VALUE_X32, VAL << RFSHSET1TMG4_REFRESH_TIMER1_START_VALUE_X32_Pos);
}

static inline uint32_t get_rfshset1tmg4_refresh_timer1_start_value_x32(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHSET1TMG4, RFSHSET1TMG4_REFRESH_TIMER1_START_VALUE_X32) >> RFSHSET1TMG4_REFRESH_TIMER1_START_VALUE_X32_Pos);
}

/****************************** Inline function for RFMSET1TMG0 register ********************************/

static inline void set_rfmset1tmg0_t_rfmpb(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFMSET1TMG0, RFMSET1TMG0_T_RFMPB, VAL << RFMSET1TMG0_T_RFMPB_Pos);
}

static inline uint32_t get_rfmset1tmg0_t_rfmpb(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFMSET1TMG0, RFMSET1TMG0_T_RFMPB) >> RFMSET1TMG0_T_RFMPB_Pos);
}

/****************************** Inline function for ZQSET1TMG0 register ********************************/

static inline void set_zqset1tmg0_t_zq_long_nop(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ZQSET1TMG0, ZQSET1TMG0_T_ZQ_LONG_NOP, VAL << ZQSET1TMG0_T_ZQ_LONG_NOP_Pos);
}

static inline uint32_t get_zqset1tmg0_t_zq_long_nop(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ZQSET1TMG0, ZQSET1TMG0_T_ZQ_LONG_NOP) >> ZQSET1TMG0_T_ZQ_LONG_NOP_Pos);
}

static inline void set_zqset1tmg0_t_zq_short_nop(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ZQSET1TMG0, ZQSET1TMG0_T_ZQ_SHORT_NOP, VAL << ZQSET1TMG0_T_ZQ_SHORT_NOP_Pos);
}

static inline uint32_t get_zqset1tmg0_t_zq_short_nop(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ZQSET1TMG0, ZQSET1TMG0_T_ZQ_SHORT_NOP) >> ZQSET1TMG0_T_ZQ_SHORT_NOP_Pos);
}

/****************************** Inline function for ZQSET1TMG1 register ********************************/

static inline void set_zqset1tmg1_t_zq_short_interval_x1024(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ZQSET1TMG1, ZQSET1TMG1_T_ZQ_SHORT_INTERVAL_X1024, VAL << ZQSET1TMG1_T_ZQ_SHORT_INTERVAL_X1024_Pos);
}

static inline uint32_t get_zqset1tmg1_t_zq_short_interval_x1024(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ZQSET1TMG1, ZQSET1TMG1_T_ZQ_SHORT_INTERVAL_X1024) >> ZQSET1TMG1_T_ZQ_SHORT_INTERVAL_X1024_Pos);
}

static inline void set_zqset1tmg1_t_zq_reset_nop(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ZQSET1TMG1, ZQSET1TMG1_T_ZQ_RESET_NOP, VAL << ZQSET1TMG1_T_ZQ_RESET_NOP_Pos);
}

static inline uint32_t get_zqset1tmg1_t_zq_reset_nop(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ZQSET1TMG1, ZQSET1TMG1_T_ZQ_RESET_NOP) >> ZQSET1TMG1_T_ZQ_RESET_NOP_Pos);
}

/****************************** Inline function for DQSOSCCTL0 register ********************************/

static inline void set_dqsoscctl0_dqsosc_enable(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DQSOSCCTL0, DQSOSCCTL0_DQSOSC_ENABLE, VAL << DQSOSCCTL0_DQSOSC_ENABLE_Pos);
}

static inline uint32_t get_dqsoscctl0_dqsosc_enable(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DQSOSCCTL0, DQSOSCCTL0_DQSOSC_ENABLE) >> DQSOSCCTL0_DQSOSC_ENABLE_Pos);
}

static inline void set_dqsoscctl0_dqsosc_interval_unit(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DQSOSCCTL0, DQSOSCCTL0_DQSOSC_INTERVAL_UNIT, VAL << DQSOSCCTL0_DQSOSC_INTERVAL_UNIT_Pos);
}

static inline uint32_t get_dqsoscctl0_dqsosc_interval_unit(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DQSOSCCTL0, DQSOSCCTL0_DQSOSC_INTERVAL_UNIT) >> DQSOSCCTL0_DQSOSC_INTERVAL_UNIT_Pos);
}

static inline void set_dqsoscctl0_dqsosc_interval(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DQSOSCCTL0, DQSOSCCTL0_DQSOSC_INTERVAL, VAL << DQSOSCCTL0_DQSOSC_INTERVAL_Pos);
}

static inline uint32_t get_dqsoscctl0_dqsosc_interval(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DQSOSCCTL0, DQSOSCCTL0_DQSOSC_INTERVAL) >> DQSOSCCTL0_DQSOSC_INTERVAL_Pos);
}

/****************************** Inline function for DERATEINT register ********************************/

static inline void set_derateint_mr4_read_interval(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATEINT, DERATEINT_MR4_READ_INTERVAL, VAL << DERATEINT_MR4_READ_INTERVAL_Pos);
}

static inline uint32_t get_derateint_mr4_read_interval(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATEINT, DERATEINT_MR4_READ_INTERVAL) >> DERATEINT_MR4_READ_INTERVAL_Pos);
}

/****************************** Inline function for DERATEVAL0 register ********************************/

static inline void set_derateval0_derated_t_rrd(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATEVAL0, DERATEVAL0_DERATED_T_RRD, VAL << DERATEVAL0_DERATED_T_RRD_Pos);
}

static inline uint32_t get_derateval0_derated_t_rrd(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATEVAL0, DERATEVAL0_DERATED_T_RRD) >> DERATEVAL0_DERATED_T_RRD_Pos);
}

static inline void set_derateval0_derated_t_rp(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATEVAL0, DERATEVAL0_DERATED_T_RP, VAL << DERATEVAL0_DERATED_T_RP_Pos);
}

static inline uint32_t get_derateval0_derated_t_rp(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATEVAL0, DERATEVAL0_DERATED_T_RP) >> DERATEVAL0_DERATED_T_RP_Pos);
}

static inline void set_derateval0_derated_t_ras_min(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATEVAL0, DERATEVAL0_DERATED_T_RAS_MIN, VAL << DERATEVAL0_DERATED_T_RAS_MIN_Pos);
}

static inline uint32_t get_derateval0_derated_t_ras_min(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATEVAL0, DERATEVAL0_DERATED_T_RAS_MIN) >> DERATEVAL0_DERATED_T_RAS_MIN_Pos);
}

static inline void set_derateval0_derated_t_rcd(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATEVAL0, DERATEVAL0_DERATED_T_RCD, VAL << DERATEVAL0_DERATED_T_RCD_Pos);
}

static inline uint32_t get_derateval0_derated_t_rcd(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATEVAL0, DERATEVAL0_DERATED_T_RCD) >> DERATEVAL0_DERATED_T_RCD_Pos);
}

/****************************** Inline function for DERATEVAL1 register ********************************/

static inline void set_derateval1_derated_t_rc(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATEVAL1, DERATEVAL1_DERATED_T_RC, VAL << DERATEVAL1_DERATED_T_RC_Pos);
}

static inline uint32_t get_derateval1_derated_t_rc(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATEVAL1, DERATEVAL1_DERATED_T_RC) >> DERATEVAL1_DERATED_T_RC_Pos);
}

static inline void set_derateval1_derated_t_rcd_write(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATEVAL1, DERATEVAL1_DERATED_T_RCD_WRITE, VAL << DERATEVAL1_DERATED_T_RCD_WRITE_Pos);
}

static inline uint32_t get_derateval1_derated_t_rcd_write(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATEVAL1, DERATEVAL1_DERATED_T_RCD_WRITE) >> DERATEVAL1_DERATED_T_RCD_WRITE_Pos);
}

/****************************** Inline function for HWLPTMG0 register ********************************/

static inline void set_hwlptmg0_hw_lp_idle_x32(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HWLPTMG0, HWLPTMG0_HW_LP_IDLE_X32, VAL << HWLPTMG0_HW_LP_IDLE_X32_Pos);
}

static inline uint32_t get_hwlptmg0_hw_lp_idle_x32(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HWLPTMG0, HWLPTMG0_HW_LP_IDLE_X32) >> HWLPTMG0_HW_LP_IDLE_X32_Pos);
}

/****************************** Inline function for SCHEDTMG0 register ********************************/

static inline void set_schedtmg0_pageclose_timer(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHEDTMG0, SCHEDTMG0_PAGECLOSE_TIMER, VAL << SCHEDTMG0_PAGECLOSE_TIMER_Pos);
}

static inline uint32_t get_schedtmg0_pageclose_timer(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHEDTMG0, SCHEDTMG0_PAGECLOSE_TIMER) >> SCHEDTMG0_PAGECLOSE_TIMER_Pos);
}

static inline void set_schedtmg0_rdwr_idle_gap(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHEDTMG0, SCHEDTMG0_RDWR_IDLE_GAP, VAL << SCHEDTMG0_RDWR_IDLE_GAP_Pos);
}

static inline uint32_t get_schedtmg0_rdwr_idle_gap(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHEDTMG0, SCHEDTMG0_RDWR_IDLE_GAP) >> SCHEDTMG0_RDWR_IDLE_GAP_Pos);
}

/****************************** Inline function for PERFHPR1 register ********************************/

static inline void set_perfhpr1_hpr_max_starve(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PERFHPR1, PERFHPR1_HPR_MAX_STARVE, VAL << PERFHPR1_HPR_MAX_STARVE_Pos);
}

static inline uint32_t get_perfhpr1_hpr_max_starve(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PERFHPR1, PERFHPR1_HPR_MAX_STARVE) >> PERFHPR1_HPR_MAX_STARVE_Pos);
}

static inline void set_perfhpr1_hpr_xact_run_length(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PERFHPR1, PERFHPR1_HPR_XACT_RUN_LENGTH, VAL << PERFHPR1_HPR_XACT_RUN_LENGTH_Pos);
}

static inline uint32_t get_perfhpr1_hpr_xact_run_length(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PERFHPR1, PERFHPR1_HPR_XACT_RUN_LENGTH) >> PERFHPR1_HPR_XACT_RUN_LENGTH_Pos);
}

/****************************** Inline function for PERFLPR1 register ********************************/

static inline void set_perflpr1_lpr_max_starve(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PERFLPR1, PERFLPR1_LPR_MAX_STARVE, VAL << PERFLPR1_LPR_MAX_STARVE_Pos);
}

static inline uint32_t get_perflpr1_lpr_max_starve(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PERFLPR1, PERFLPR1_LPR_MAX_STARVE) >> PERFLPR1_LPR_MAX_STARVE_Pos);
}

static inline void set_perflpr1_lpr_xact_run_length(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PERFLPR1, PERFLPR1_LPR_XACT_RUN_LENGTH, VAL << PERFLPR1_LPR_XACT_RUN_LENGTH_Pos);
}

static inline uint32_t get_perflpr1_lpr_xact_run_length(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PERFLPR1, PERFLPR1_LPR_XACT_RUN_LENGTH) >> PERFLPR1_LPR_XACT_RUN_LENGTH_Pos);
}

/****************************** Inline function for PERFWR1 register ********************************/

static inline void set_perfwr1_w_max_starve(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PERFWR1, PERFWR1_W_MAX_STARVE, VAL << PERFWR1_W_MAX_STARVE_Pos);
}

static inline uint32_t get_perfwr1_w_max_starve(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PERFWR1, PERFWR1_W_MAX_STARVE) >> PERFWR1_W_MAX_STARVE_Pos);
}

static inline void set_perfwr1_w_xact_run_length(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PERFWR1, PERFWR1_W_XACT_RUN_LENGTH, VAL << PERFWR1_W_XACT_RUN_LENGTH_Pos);
}

static inline uint32_t get_perfwr1_w_xact_run_length(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PERFWR1, PERFWR1_W_XACT_RUN_LENGTH) >> PERFWR1_W_XACT_RUN_LENGTH_Pos);
}

/****************************** Inline function for TMGCFG register ********************************/

static inline void set_tmgcfg_frequency_ratio(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->TMGCFG, TMGCFG_FREQUENCY_RATIO, VAL << TMGCFG_FREQUENCY_RATIO_Pos);
}

static inline uint32_t get_tmgcfg_frequency_ratio(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->TMGCFG, TMGCFG_FREQUENCY_RATIO) >> TMGCFG_FREQUENCY_RATIO_Pos);
}

/****************************** Inline function for RANKTMG0 register ********************************/

static inline void set_ranktmg0_diff_rank_rd_gap(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RANKTMG0, RANKTMG0_DIFF_RANK_RD_GAP, VAL << RANKTMG0_DIFF_RANK_RD_GAP_Pos);
}

static inline uint32_t get_ranktmg0_diff_rank_rd_gap(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RANKTMG0, RANKTMG0_DIFF_RANK_RD_GAP) >> RANKTMG0_DIFF_RANK_RD_GAP_Pos);
}

static inline void set_ranktmg0_diff_rank_wr_gap(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RANKTMG0, RANKTMG0_DIFF_RANK_WR_GAP, VAL << RANKTMG0_DIFF_RANK_WR_GAP_Pos);
}

static inline uint32_t get_ranktmg0_diff_rank_wr_gap(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RANKTMG0, RANKTMG0_DIFF_RANK_WR_GAP) >> RANKTMG0_DIFF_RANK_WR_GAP_Pos);
}

/****************************** Inline function for RANKTMG1 register ********************************/

static inline void set_ranktmg1_wr2rd_dr(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RANKTMG1, RANKTMG1_WR2RD_DR, VAL << RANKTMG1_WR2RD_DR_Pos);
}

static inline uint32_t get_ranktmg1_wr2rd_dr(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RANKTMG1, RANKTMG1_WR2RD_DR) >> RANKTMG1_WR2RD_DR_Pos);
}

static inline void set_ranktmg1_rd2wr_dr(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RANKTMG1, RANKTMG1_RD2WR_DR, VAL << RANKTMG1_RD2WR_DR_Pos);
}

static inline uint32_t get_ranktmg1_rd2wr_dr(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RANKTMG1, RANKTMG1_RD2WR_DR) >> RANKTMG1_RD2WR_DR_Pos);
}

/****************************** Inline function for PWRTMG register ********************************/

static inline void set_pwrtmg_powerdown_to_x32(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PWRTMG, PWRTMG_POWERDOWN_TO_X32, VAL << PWRTMG_POWERDOWN_TO_X32_Pos);
}

static inline uint32_t get_pwrtmg_powerdown_to_x32(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PWRTMG, PWRTMG_POWERDOWN_TO_X32) >> PWRTMG_POWERDOWN_TO_X32_Pos);
}

static inline void set_pwrtmg_selfref_to_x32(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PWRTMG, PWRTMG_SELFREF_TO_X32, VAL << PWRTMG_SELFREF_TO_X32_Pos);
}

static inline uint32_t get_pwrtmg_selfref_to_x32(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PWRTMG, PWRTMG_SELFREF_TO_X32) >> PWRTMG_SELFREF_TO_X32_Pos);
}

/****************************** Inline function for LNKECCCTL0 register ********************************/

static inline void set_lnkeccctl0_wr_link_ecc_enable(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCCTL0, LNKECCCTL0_WR_LINK_ECC_ENABLE, VAL << LNKECCCTL0_WR_LINK_ECC_ENABLE_Pos);
}

static inline uint32_t get_lnkeccctl0_wr_link_ecc_enable(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCCTL0, LNKECCCTL0_WR_LINK_ECC_ENABLE) >> LNKECCCTL0_WR_LINK_ECC_ENABLE_Pos);
}

static inline void set_lnkeccctl0_rd_link_ecc_enable(LPDDR5_REGB_FREQ0_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCCTL0, LNKECCCTL0_RD_LINK_ECC_ENABLE, VAL << LNKECCCTL0_RD_LINK_ECC_ENABLE_Pos);
}

static inline uint32_t get_lnkeccctl0_rd_link_ecc_enable(LPDDR5_REGB_FREQ0_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCCTL0, LNKECCCTL0_RD_LINK_ECC_ENABLE) >> LNKECCCTL0_RD_LINK_ECC_ENABLE_Pos);
}

#endif // __LPDDR5_REGB_FREQ0_CH0_H__
